Flash EEPROM cell having gap between floating gate and drain for

Details Flash EEPROM cell having gap between floating gate and drain for Flash EEPROM cell having gap between floating gate and drain for

1993-10-18

1995-01-03

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257322, 257408, 257900, H01L 2978

Patent

active

053789091

ABSTRACT:
A flash or block erase electrically erasable programmable read-only memory (EEPROM) cell (10) includes a substrate (12) having a channel region (22), and a source (28) and a drain (32) formed in the substrate (12) on opposite sides of the channel region (22). A first oxide layer (19), a floating gate (20), a second oxide layer (24) and a control gate (26) are formed over the channel region (22). The cell (10) is programmed by hot electron injection from the drain (32) into the floating gate (20), and erased by Fowler-Nordheim tunneling from the floating gate (20) to the source (28). A gap (36) is provided between a sidewall (20a) of the floating gate (20) and the drain (32) to increase the electric field in the drain depletion region. An oxide sidewall spacer (38) is formed on the first oxide layer (19) in the gap (36) which traps electrons. The gap (36) and sidewall spacer (38) increase the hot electron injection efficiency, and enable programming to be accomplished at high speed, with low applied voltages and at high temperatures.

REFERENCES:
patent: 4376947 (1983-03-01), Chiu et al.
patent: 4663645 (1987-05-01), Komori et al.
patent: 4939558 (1990-07-01), Smayling et al.
patent: 5032881 (1991-07-01), Sardo et al.
H. Kume, et al., "A Flash-Erase EEPROM Cell with an Asymmetric Source and Drain Structure", IEEE-IEDM 87, pp. 560-563.
R. Kazerounian, et al., "A 5 Volt High Density Poly-Poly Erase Flash EPROM Cell", IEEE-IEDM 88, pp. 436-439.

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