Static information storage and retrieval – Read/write circuit – Erase
Patent
1989-10-23
1991-12-31
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Erase
365185, 365200, G11C 1140
Patent
active
050776916
ABSTRACT:
A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V.sub.CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.
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Chang Chi
Haddad Sameer S.
Matalvo Antonio
Van Buskirk Michael A.
Advanced Micro Devices , Inc.
Popek Joseph A.
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