Static information storage and retrieval – Read/write circuit – Including signal comparison
Patent
1993-08-23
1994-10-25
Clawson, Jr., Joseph E.
Static information storage and retrieval
Read/write circuit
Including signal comparison
365185, 36518909, 365210, 365218, 365236, 365900, G11C 1140
Patent
active
053595580
ABSTRACT:
An improved over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance. Sensing circuitry (20) is used to detect column leakage current indicative of an over-erased bit during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell. A data input buffer circuit (26) is used to compare the logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal. A pulse counter (30) is coupled to the data input buffer circuit for counting a plurality of programming pulses applied thereto. The data input buffer circuit selectively connects only certain ones of the columns of bit lines to the pulse counter in which the bit match signal is at a high logic level so as to program back over-erased memory cells connected to only the certain ones of the columns of bit lines.
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Chang Chung K.
Chen Johnny C.
Cleveland Lee E.
Van Buskirk Michael A.
Advanced Micro Devices , Inc.
Chin Davis
Clawson Jr. Joseph E.
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