Flash EEPROM and EPROM arrays with select transistors within the

Details Flash EEPROM and EPROM arrays with select transistors within the Flash EEPROM and EPROM arrays with select transistors within the

1994-03-11

1996-09-17

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257322, 36518506, H01L 29788

Patent

active

055571247

ABSTRACT:
Flash EEPROM array and EPROM arrays are described. The EEPROM array has EEPROM areas with arrays of EEPROM transistors, at least one control area per EEPROM area and columns of a first polysilicon layer traversing the EEPROM and control areas. The columns are divided into even and odd columns. Each control area is divided into upper, middle and lower areas and each control area includes the following: a) within the middle area, cross-lines of the first polysilicon extending from each even to the next odd column; b) four rows of a second polysilicon layer, laid down after the columns and cross-lines of the first polysilicon layer within the control areas are removed; and c) isolating oxide elements laid down prior to the first polysilicon layer and self-aligned to it before it is removed. The isolating oxide elements are located under every odd column in the upper area, under each column in the middle area, under each odd column in one row of the lower area and under each even column in the other row of the lower area. Bit line select and erase select rows are in the upper and middle areas, respectively, and two column select rows are in the lower area. Erase select transistors are formed at the intersections of the removed cross-lines with the erase select row of second polysilicon, bit line select transistors are formed at the intersections of removed even columns with the bit line select row of second polysilicon, and column select transistors are formed at intersections of the column select rows of second polysilicon with the removed columns wherever no isolating oxide elements exist. The EPROM array has a similar structure but does not include the erase select transistors. The select transistors are n-channel transistors each formed of a) a channel, b) two diffusion bit lines bordering the channel and aligned to a first, subsequently removed, polysilicon layer and c) a second polysilicon layer extending between and over the two diffusion bit lines.

REFERENCES:
patent: 4267632 (1981-05-01), Shappir
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5151375 (1993-09-01), Kazerounian et al.
patent: 5204835 (1993-04-01), Eitan
patent: 5379254 (1995-01-01), Chang
patent: 5402372 (1995-03-01), Bergemont
W. Kammerer et al., "A New Virtual Ground Array Architecture For Very High Speed, High Density EPROMS", VLSI Circuits Symposium, Japan, 1991.
S. Cagnina et al., "A 0.85 .mu.m Double Metal CMOS Technology for 5V Flash EEPROM Memories with Sector Erase", 12th NVSM Workshop, Monterey, CA, 1992 .

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