Static information storage and retrieval – Read/write circuit
Patent
1992-03-25
1994-12-13
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
365154, 365156, 365218, 365190, 257903, 257904, G11C 700
Patent
active
053734661
ABSTRACT:
A reset mechanism for a random access memory array comprises an auxiliary reset circuit, which does not require modification of the contents of the memory itself. For a random access memory capable of storing M, N-bit words, the auxiliary mechanism includes a plurality of M reset state circuits that are respectively associated with the M words of memory. The reset state circuit preferably comprises an additional `resetable` memory cell for each word of memory, which is integrated within the structure of the memory itself. In order to reset one or more words of memory, the associated reset state circuits are placed in a reset state-representative condition. The state of each reset state circuit is used to controllably mask (e.g. is logically ANDed with) the contents of its associated word of memory, whenever that word is read out. If the reset memory cell has been cleared, then regardless of the contents of its associated word in memory, the mask will cause the addressed memory word to be output as all zeros. Whenever a new word value is written to memory, its associated reset state circuit is simultaneously accessed and a valid or non-reset representative `1` bit is stored in that reset state circuit. Subsequently, when that word is read out from memory, the (`1`) value of the mask bit stored in its associated reset cell will cause the contents of the word to be output as is.
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Landeta David S.
Longway Charles W. T.
Young William R.
Harris Corporation
LaRoche Eugene R.
Tran Andrew Q.
Wands Charles E.
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