Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-25
2010-11-09
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C430S030000
Reexamination Certificate
active
07831954
ABSTRACT:
An embodiment of the present invention provides a system that computes the effect of perturbations to a pattern layout during an OPC process. During operation, the system receives a pattern layout and a set of lithography model kernels. The system then obtains a set of convolved patterns by convolving the pattern layout with each of the set of lithography model kernels. The system additionally receives a perturbation pattern to be added onto the pattern layout. Next, for a query location on the pattern layout, the system obtains a set of convolution values at the query location by using model flash lookup tables to convolve the perturbation pattern with the set of lithography model kernels. The system then updates the set of convolved patterns at the query location to account for the effect of the perturbation pattern by combining the set of convolution values with the set of convolved patterns.
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Cranford Micheal
Rieger Michael L.
Stirniman John P.
Park Vaughan Fleming & Dowler LLP
Rossoshek Helen
Synopsys Inc.
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