Flag generation scheme for FIFOs

Details Flag generation scheme for FIFOs Flag generation scheme for FIFOs

1999-08-10

2002-08-27

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C710S054000, C365S189070, C365S189120, C365S220000, C365S221000

Reexamination Certificate

active

06442657

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to FIFO buffers generally, and more particularly, to a method for generating FIFO status flags in a hybrid embedded Dual-Port/FIFO memory.
BACKGROUND OF THE INVENTION
Conventional flag generation circuits used in first-in first-out (FIFO) memories can use four dedicated flag address counters. Conventional depth expansion logic is implemented as part of the flag logic circuit. Consequently, changes in the depth expansion logic are made within the flag logic.
Referring to
FIG. 1
, a conventional circuit
10
for generating status flags is shown. The circuit
10
comprises an array read address counter
12
, an array write address counter
14
, a memory array
16
, a flag address block
18
, and a flag logic block
20
. The circuit
10
increases the die size due to the required separation of the array address counters
12
and
14
from the flag address circuit
18
.
The array read address counter
12
is coupled to the memory array
16
. An enable read signal ENRCLK is presented to the array read address counter
12
as well as to the flag address circuit
18
. The array write address counter
14
is also coupled to the memory array
16
. An enable write signal ENWCLK is presented to the array write address counter
14
as well as to the flag address circuit
18
.
The flag/array address circuit
18
comprises a read address counter
22
, a read address+1 counter
24
, a write address
10
counter
26
, and a write address+1 counter
28
. The enable read signal ENRCLK is presented to the read address counter
22
and the read address+1 counter
24
. The read address counter
22
presents a read signal RADDRESS in response to the enable read signal ENRCLK. The read address+1 counter
24
presents read plus one signal RADDRESS+1 in response to the enable read signal ENRCLK. The enable write signal ENWCLK is presented to the write address counter
26
and the write address+1 counter
28
. The write address counter
26
presents a write signal WADDRESS in response to the enable write signal ENWCLK. The write address+1 counter
28
presents a write plus one signal WADDRESS+1 in response to the enable write signal ENWCLK.
The flag logic
20
presents a plurality of control signals in response to the signal RADDRESS, the signal RADDRESS+1, the signal WADDRESS, the signal WADDRESS+1, a depth control signal DEPTH CONTROL and an offset signal OFFSET. The flag logic circuit
20
comprises an empty/full flag decoder
32
, a half full flag and depth control logic
34
, and a programmable flag and depth control logic
36
, which each receive the signal RADDRESS, the signal RADDRESS+1, the signal WADDRESS, the signal WADDRESS+1, and the signal DEPTH CONTROL. The programmable flag and depth control logic
36
receives an additional offset signal OFFSET. To implement depth configuration, the signal DEPTH CONTROL is used within the flag logic circuit
20
. The depth control logic is implemented as part of the flag logic circuit
20
. Therefore, changes to the depth expansion must be made within the flag logic circuit
20
.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a memory, a flag/array address circuit and a flag logic circuit. The memory may be configured to read and write data in response to one or more memory address signals. The flag/array address circuit may be configured to present one or more flag address signals in response to (i) one or more enable signals and (ii) a control signal. The flag logic circuit may be configured to present one or more logic flags in response to the one or more flag address signals.
The objects, features and advantages of the present invention may include implementing a flag generation scheme that may (i) provide a highly efficient architecture for generating flag logic addresses and array addresses, (ii) save real estate in an embedded design by sharing the array address with the flag address, (iii) implement the depth control circuitry separately from the flag logic circuitry, (iv) implement a depth control circuit that may be programmed without changing the flag logic, and/or (v) provide a portable flag generation block that may easily augment a Dual-Port design for use as a FIFO.


REFERENCES:
patent: 5587953 (1996-12-01), Chung
patent: 5627797 (1997-05-01), Hawkins et al.
patent: 5712992 (1998-01-01), Hawkins et al.
patent: 5809339 (1998-09-01), Hawkins et al.
patent: 5850568 (1998-12-01), Hawkins et al.
patent: 5852748 (1998-12-01), Hawkins et al.
patent: 5991834 (1999-11-01), Hawkins et al.
patent: 6016403 (2000-01-01), Hawkins et al.
patent: 6070203 (2000-05-01), Hawkins et al.
64K/128Kx9 Deep Sync FIFOs w/Retransmit & Depth Expansion, Cypress Preliminary CY7C4282 and CY7C4292, Cypress Semiconductor Corporation, Revised Nov. 6, 1997, pp. 1-16.

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