Flag circuit for memory

Details Flag circuit for memory Flag circuit for memory

1991-02-22

1994-04-26

Wambach, Margaret Rose

Static information storage and retrieval

Read/write circuit

365201, 36523001, G11C 802

Patent

active

053073134

ABSTRACT:
In a semiconductor integrated circuit for switching various functions in accordance with "H"/"L" level of a read output from EPROM cells or the like, a state of memory cells incorporated in the semiconductor is detected to switch a function state. The semiconductor integrated circuit is free from an inoperative state caused by indefinite values of an initial state (erasure state) as of the EPROM cells and the like, or is free from a state in which only a predetermined operation is performed. When a writing operation is performed to EPROM cells and the like in an initial state in advance, a function test for a semiconductor integrated circuit can be normally performed. A test time can be largely decreased compared with that of a conventional technique, and a production cost can be largely reduced.

REFERENCES:
patent: 4365312 (1982-12-01), Nakano et al.
patent: 5016220 (1991-05-01), Yamagata
patent: 5023718 (1991-06-01), Soloff
patent: 5088063 (1992-02-01), Matsuda et al.
patent: 5151877 (1992-09-01), Brennan

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