Fixed-spacing parity insertion for FEC (Forward Error...

Details Fixed-spacing parity insertion for FEC (Forward Error... Fixed-spacing parity insertion for FEC (Forward Error...

2008-01-29

2011-12-27

Baker, Stephen (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

08086930

ABSTRACT:
Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities.

REFERENCES:
patent: 6199190 (2001-03-01), Wan
patent: 6567938 (2003-05-01), Wan
patent: 7409622 (2008-08-01), Lu et al.
patent: 7434138 (2008-10-01), Lin et al.
patent: 7484168 (2009-01-01), Siegel et al.
patent: 2005/0053168 (2005-03-01), Song et al.

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