Fixed phase clock and strobe signals in daisy chained chips

Details Fixed phase clock and strobe signals in daisy chained chips Fixed phase clock and strobe signals in daisy chained chips

2006-04-18

2006-04-18

Phan, Trong (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S233100, C365S194000

Reexamination Certificate

active

07031221

ABSTRACT:
In some embodiments, a chip includes first and second ports to provide first and second received data signals and first and second received strobe signal, respectively. An internal clock signal has a fixed phase relationship to the first received strobe signal and the second received strobe signal has an arbitrary phase relationship with the internal clock signal. First and second write blocks latch the first and second received data signals synchronously with the first and second received strobe signals, respectively. Other embodiments are described and claimed.

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