Fixed duty cycle clock generator

Pulse or digital communications – Spread spectrum – Direct sequence

Patent

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Details

328136, 377107, H04L 700

Patent

active

051014190

ABSTRACT:
There is disclosed an improved clock generator responsive to a first clock signal having a frequency f.sub.1 and a second clock signal having a frequency f.sub.2, wherein f.sub.2 is equal to nf.sub.1. The clock generator provides a fixed duty cycle clock signal having a period equal to n complete cycles of the second clock signal and being at a first level for m complete cycles of the second clock signal and a second level for n-m complete cycles of the second clock signal. The clock generator includes a counter for counting half-cycles of the second clock signal to derive the first and second levels, and a flip-flop for establishing a timing condition responsive to the first clock signal. The clock generator further includes an inhibit circuit coupled to the counter for enabling the counter to begin a new counting period in response to the counter counting n complete cycles of the second clock signal and the establishment of the timing condition. The clock generator inhibit circuit guarantees a consistent duty cycle signal output immune to variations of the period of the first clock signal to as low as n-1/2 complete cycles of the second clock signal.

REFERENCES:
patent: 3663885 (1972-05-01), Stewart
patent: 4214270 (1980-07-01), Morito
patent: 4622481 (1986-11-01), Nortrup

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