Five volt tolerant input scheme using a switched CMOS pass gate

Details Five volt tolerant input scheme using a switched CMOS pass gate Five volt tolerant input scheme using a switched CMOS pass gate

2002-07-12

2004-07-27

Nelms, David (Department: 2818)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S021000, C326S056000, C326S080000

Reexamination Certificate

active

06768339

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to voltage protection circuits generally and, more particularly, to a five volt tolerant input scheme using a switched CMOS pass gate.
BACKGROUND OF THE INVENTION
In a Small Computer Systems Interface (SCSI) bus environment, voltages of 5.5V are sometimes present on the input I/O pads. In order to maintain the reliability of the thick oxide I/O transistors, an input is used to limit the maximum voltage drop across the gate oxide to 3.63V (i.e., the supply voltage VDD). Furthermore, SCSI design specifications specify that a receiver be able to detect a low to high threshold voltage of 1.9V. Therefore, an input signal of 1.9V should pass through to the receiver with no amplitude attenuation.
In conventional designs, a native pass gate with its gate tied to the supply voltage VDD is used to limit the input voltage to VDD while cleanly passing input signals to the receiver with input swings up to VDD. A native NMOS transistor has a significantly smaller threshold voltage (e.g., 0 to 0.2 v) than a typical NMOS transistor (e.g., 0.7V). However, body effect can make threshold voltages even larger (e.g., 0.5V for native and 1.2V for typical NMOS). Hence, a native device can pass signals nearly from (VDD−0.5 v) to VSS.
Native devices are not available in all process technologies. When native devices are not available in a particular process, an alternate solution needs to be implemented. Even if a native device is available for a particular process, the native device can add to the overall cost of a design.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising (i) an input circuit configured to provide a predetermined voltage tolerance in response to a plurality of control signals and (ii) a control circuit configured to generate the plurality of control signals in response to one or more input signals.
The objects, features and advantages of the present invention include providing a voltage protection circuit that may (i) provide a five volt tolerant input, (ii) be implemented using a switched CMOS pass gate, and/or (iii) be implemented in process technologies with no native devices available.


REFERENCES:
patent: 5825206 (1998-10-01), Krishnamurthy et al.
patent: 6181165 (2001-01-01), Hanson et al.
patent: 6310492 (2001-10-01), Ikoma et al.
patent: 6577163 (2003-06-01), Waldrip et al.

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