Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1998-01-29
2000-11-21
Tokar, Michael
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 57, 326 81, H03K 190175, H03K 1900
Patent
active
061508438
ABSTRACT:
A 5 volt tolerant I/O buffer circuit is coupled to a power supply terminal of a predetermined power supply voltage, for driving an I/O pad to a logic state depending on an input signal and an output enable signal. The I/O buffer circuit minimizes current flow into the power supply terminal when the pad is coupled to a voltage greater than the predetermined power supply voltage. A driver transistor of a first type is formed within a diffusion well and is coupled to the predetermined power supply voltage and to the pad. First and second terminals of a protection transistor are coupled to respective ones of the predetermined power supply voltage and the diffusion well. Circuitry is provided for, when the output enable signal is active, turning on the protection transistor so as to couple the predetermined power supply voltage to the diffusion well, regardless of a voltage level of the pad. A single protection transistor is sufficient to prevent current leakage through the parasitic PN diode.
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Ahmad Waseem
Shiffer James D.
Chang Daniel D.
Tokar Michael
VLSI Technology Inc.
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