Five transistor SRAM cell

Details Five transistor SRAM cell Five transistor SRAM cell

1998-10-05

2000-03-28

Nguyen, Viet Q.

Static information storage and retrieval

Systems using particular element

Flip-flop

36518901, 36518905, 36518908, G11C 1141

Patent

active

060440104

ABSTRACT:
A five transistor static random-access-memory (SRAM) cell is disclosed. The cell includes two cross-coupled inverters, each having two transistors, and a single n-channel transistor switch. The cell is programmed by first forcing the node connected between the inverters and the switch to a predefined logic state that is maintained by a p-channel transistor of an inverter, and then passing the voltage that corresponds to the logic state to be programmed. If the logic state to be programmed matches the predefined logic state, no significant charge is transferred. If the logic state to be programmed does not match the predefined logic state, then the n-channel transistor switch overpowers the p-channel transistor to change the predefined logic state.

REFERENCES:
patent: 5003513 (1991-03-01), Porter et al.
patent: 5053996 (1991-10-01), Slemmer
patent: 5386379 (1995-01-01), Ali-Yahia et al.
patent: 5400294 (1995-03-01), Srinivasan et al.
patent: 5583821 (1996-12-01), Rose et al.
patent: 5633828 (1997-05-01), McClure et al.
patent: 5691935 (1997-11-01), Douglass
patent: 5764900 (1988-08-01), Bader et al.
patent: 5850359 (1998-12-01), Liu
patent: 5923582 (1999-07-01), Voss

Affiliated with

Also associated with

Rating

Five transistor SRAM cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Five transistor SRAM cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Five transistor SRAM cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1331704