Five transistor memory cell with shared power line

Details Five transistor memory cell with shared power line Five transistor memory cell with shared power line

1995-01-24

1995-09-26

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365174, G11C 1140

Patent

active

054539501

ABSTRACT:
Static random access memory cells (SRAMS) containing five MOS transistors are configured in a memory array such that only three bitlines are required for two cells. A first bitline is coupled to a first side of a first memory cell, and a second bitline is coupled to a first side of the second memory cell. The first and second memory cells share either a common power bitline or a common ground bitline. A control circuit executes a special write operation to write a low logic level on the second side of the memory cells. The control circuit is coupled to the first, second, and third bitlines to generate a first differential voltage across the memory cells that is lower than the operating voltage on the third bitline and to generate a second voltage lower than the operating voltage on the second bitline when storing a low logic level on the second side of the first storage cell. To perform a special write operation on the second storage cell, the control circuit generates the first differential voltage on the third bitline and the second voltage on the first bitline.

REFERENCES:
patent: 4724530 (1988-02-01), Dingwall
patent: 4872141 (1989-10-01), Plus et al.
patent: 5301147 (1994-04-01), Guo et al.
patent: 5315545 (1994-05-01), Guo et al.
patent: 5353251 (1994-10-01), Uratani et al.

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