Five transistor CMOS memory cell including diodes

Details Five transistor CMOS memory cell including diodes Five transistor CMOS memory cell including diodes

1978-10-03

1988-02-09

Larkins, William D.

Static information storage and retrieval

Systems using particular element

Flip-flop

357 237, 357 42, 357 59, G11C 1140, H01L 2712

Patent

active

047245301

ABSTRACT:
The memory cell is a five transistor cell formed with complementary symmetry metal oxide (CMOS) semiconductor insulated gate field effect transistors (IGFETs) in the silicon-on-sapphire (SOS) technology with doped polycrystalline interconnects using buried contacts. Diodes are formed where doped polycrystalline silicon lines form buried contacts to underlying silicon epitaxial regions of opposite conductivity type and where silicon epitaxial regions of opposite conductivity type contact one another. The presence of these diodes has been shown by the inventor to not be detrimental to the operation of the memory cell.

REFERENCES:
patent: 3521242 (1970-07-01), Katz
patent: 3990056 (1976-11-01), Luisi et al.
patent: 4189782 (1980-02-01), Dingwall
patent: 4196443 (1980-04-01), Dingwall
RCA COS/MOS Integrated Circuits Manual, Technical Series CMS-270, RCA/Solid State Division, Somerville, N.J. (1971), p. 22.

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