Five square folded-bitline DRAM cell

Details Five square folded-bitline DRAM cell Five square folded-bitline DRAM cell

1994-12-28

2001-06-26

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S900000, C257S401000

Reexamination Certificate

active

06252267

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to DRAM cell design and semiconductor interconnection techniques. More particularly, it relates to a conductive sidewall rail wordline for a DRAM cell and to a cell design with significantly diminished dimensions.
BACKGROUND OF THE INVENTION
Large numbers of DRAM cells must be interconnected with wordlines, and wordlines and spaces between wordlines are determinative of the size of a folded-bitline cell. Typically, wordlines are formed as thin films of a conductor, such as aluminum or polysilicon, deposited on insulating materials on the semiconductor surface and defined as lines photolithographically. Efforts to shrink wordlines and the spaces between wordlines are limited since both line widths and spaces cannot practically be made smaller than the minimum photolithographically defined line. While it is possible to decrease the line width, for example, decreasing the line width usually increases the line-to-line spacing and so the overall wordline pitch is not improved. The cost of decreasing the photolithographic minimum dimension is high, and each such effort has defined succeeding generations of semiconductor products. In each generation of DRAM cells, the photolithographically defined wordline and its associated space have each thus been formed at the photolithographic minimum dimension.
In the folded-bitline DRAM cell design, both an active and a passing word line pass through each cell, as illustrated in commonly assigned U.S. Pat. No. 4,801,988 (“the '988 patent”), issued to D. M. Kenney, entitled “Semiconductor Trench Capacitor Cell with Merged Isolation and Node Trench Construction,” and shown here in FIG.
1
. Crossing over trench capacitors
505
A and
510
A for a pair of cells in
FIG. 1
, are wordlines
515
A and
520
A. The space required for such a DRAM cell is a minimum dimension for each of the two wordlines in each cell and an additional minimum dimension for each space between each wordline. Thus the total minimum length of the traditional cell is 4 minimum dimensions. The width of the cell is at least two minimum dimensions, of which one is for the components in the cell and the other is for a thick isolation (a trench capacitor can be a part of this isolation) in the space between cells. Thus, the minimum area of a traditional cell has been 8 square minimum dimensions, or 8 squares.
One approach to avoid the photolithographic limit is to provide a wordline formed of a conductive sidewall rail. The width of such rails is determined by the thickness of the deposited conductor, and this thickness can be significantly less than a minimum photolithographic dimension. Commonly assigned U.S. Pat. No. 5,202,272 (“the '272 patent”), issued to Hsieh, entitled “Field Effect Transistor Formed With Deep-Submicron Gate,” and U.S. Pat. No. 5,013,680 (“the '680 patent”), issued to Lowrey, entitled “Process for Fabricating a DRAM Array Having Feature Widths that Transcend the Resolution Limit of Available Photolithography,” teach methods of using a subminimum dimension conductive sidewall spacer rail to form a wordline.
One problem encountered in the use of such subminimum dimension spacer rail wordlines is the difficulty of precisely controlling the length of the device and the extent of lateral diffusion of the source and drain. For example, small variations of spacer thickness or lateral diffusion can result in a large variation in the length of the subminimum dimension channel. The result can be large leakage currents on the one hand and degraded performance on the other. The present invention avoids the difficulties of the subminimum dimension sidewall spacer rail wordlines of the prior art.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a folded-bitline DRAM cell with a photolithographically formed gate, the cell having an area of less than 8 squares.
It is a feature of the present invention that a subminimum dimension spacer rail wordline links approximately minimum dimension individual gate segments.
It is a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension spacer rail gate connector.
These and other objects of the invention are accomplished by semiconductor structure comprising a transistor having a gate comprising an individual segment of gate conductor that is substantially coextensive with the thin dielectric of the gate stack. A connector is in contact with the segment gate, the connector being a conductive spacer rail.
Another aspect of the invention involves a DRAM cell comprising a transistor having a gate comprising an individual segment of gate conductor that is substantially coextensive with the thin dielectric of the gate stack. A wordline is in contact with the segment gate, the wordline being a conductive spacer rail.
Applicant recognized that, in a folded-bitline arrangement, the use of a subminimum dimension spacer rail wordline permits saving 1½ minimum dimensions along the long direction of the cell, reducing this length from 4 minimum dimensions to 2½ minimum dimensions, thereby reducing the area of the DRAM cell from 8 squares to 5 squares, a 37.5% reduction in cell area. In addition, because the gate function and the strapping function of the wordline are separated in the present invention, the advantages of a polysilicon gate can be retained while high conductivity materials, such as tungsten or aluminum can be used to form the subminimum dimension wordlines, retaining high conductivity for the wordlines as well.
Another aspect of the invention is accomplished by a method comprising the steps of forming a gate of a transistor comprising an individual segment of gate conductor; forming a mandrel having a sidewall over the gate conductor; forming a conductive material adjacent the sidewall and in contact with the gate conductor; and directional etching the conductive material to form a spacer rail connector.
These and other objects, features, and advantages of the invention will become apparent from the drawings and description of the invention.


REFERENCES:
patent: 4801988 (1989-01-01), Kenney
patent: 4812885 (1989-03-01), Riemenschneidrr
patent: 5013680 (1991-05-01), Lowrey et al.
patent: 5023679 (1991-06-01), Shibata
patent: 5146291 (1992-09-01), Watabe et al.
patent: 5160987 (1992-11-01), Pricer et al.
patent: 5202272 (1993-04-01), Hsieh et al.
patent: 5214603 (1993-05-01), Dhong et al.
patent: 5264716 (1993-11-01), Kenney
patent: 5493130 (1996-02-01), Dennison et al.
patent: 5498889 (1996-03-01), Hayden
patent: 5539229 (1996-07-01), Noble, Jr. et al.

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