Five device merged transistor RAM cell

Details Five device merged transistor RAM cell Five device merged transistor RAM cell

1979-07-30

1981-09-29

Zazworsky, John

Static information storage and retrieval

Systems using particular element

Flip-flop

307288, 357 44, 357 92, G11C 1140

Patent

active

042926750

ABSTRACT:
A five device RAM cell comprising a four device Merged Transistor Logic (MTL) cell plus a separate sense line and a fifth bipolar transistor device having a collector connected to one node of the cell, a base connected to the other node of the cell, and an emitter connected to the sense line.

REFERENCES:
patent: 3815106 (1974-06-01), Wiedmann
patent: 3986178 (1976-10-01), McElroy et at.
patent: 4081697 (1978-03-01), Nakano
patent: 4150392 (1979-04-01), Nonaka
S. K. Wiedmann, MTL Storage Cell, IBM Technical Disclosure Bulletin, vol. 21, No. 1, Jun., 1978, pp. 231-232.

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