First-in-first-out synchronizer

Details First-in-first-out synchronizer First-in-first-out synchronizer

1998-05-15

2001-03-27

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C709S241000, C713S400000

Reexamination Certificate

active

06208703

ABSTRACT:

BACKGROUND
The present invention concerns data communication and pertains particularly to a first-in-first-out synchronizer.
When a circuit interfaces two separate systems with non-correlated and non-synchronous clocks, metastable states can result when a signal from one system is sampled using the clock from the other system. This happens, for example, when a signal from the first system is sampled with the clock of the second system when the signal from the first system is in transition.
In order to alleviate the metastable problem, synchronization circuits are used to provide synchronization for systems with non-correlated and non-synchronous clocks.
Generally the synchronization systems provide a handshake that is independent of the phase and frequency of the producer and consumer clocks.
The conventional way of performing this handshaking process is to fully interlock, via two signals that cross the clock boundary and that must therefore be synchronized, the producer and consumer state machines. The design of these state machines is tricky and has the potential to create subtle problems especially when it is important to operate the handshake at the maximum possible rate.
This interlocking is needed not only in the case where the two clocks are asynchronous but also when two clocks differ in frequency so that one period in a clock domain corresponds to a different number of periods in the other clock domain.
One system that provides for synchronization is set out in U.S. Pat. No. 4,873,703, issued to Douglas Crandall et al., for SYNCHRONIZING SYSTEM. This system provides for reliably passing data across a boundary between two independent, not-correlated clocks. The system reduces occurrence of errors due to asynchronous samplings. The system is implemented as a two port memory and performs a handshake between the two non-correlated clock systems. For further information on synchronizing system of these types, see also, Vince Cavanna,
The FIFO/Synchronizer: A Novel FIFO Architecture with Robust Performance as a Synchronizer, Proceedings of On-Chip System Design Conference, Design Supercon
97.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a one stage first-in-first-out synchronizer is presented. The one stage first-in-first-out synchronizer includes a producer side and a consumer side. The producer side includes a first write buffer, a not full output, a write input, a second write buffer and a write clock input. The first write buffer stores a write pointer. The not full output indicates whether new data may be written. The write input is asserted to write data. The second write buffer receives as input a read pointer. The write clock input is used to provide a clock signal to the first write buffer and the second write buffer. The consumer side includes a first read buffer, a not empty output, a read input, a second read buffer, and a read clock input. The first read buffer stores the read pointer. The not empty output indicates whether stored data may be read. The read input is asserted to read data. The second read buffer receives as input the write pointer. The read clock input is used to provide a clock signal to the first write buffer and the second write buffer.
The one stage first-in-first-out synchronizer includes, for example, a register for buffering data. The register includes a clock input, connected to the write clock input, and a load input connected to an input of the first write buffer. Alternatively, the register for buffering data may be located external to the one stage first-in-first-out synchronizer. The one stage first-in-first-out synchronizer may also be utilized where there is no data buffering but data is transferred directly from a producer to a consumer without buffering the data.
In a first preferred embodiment of the present invention, the one stage first-in-first-out synchronizer includes a first write flip-flop, a first read flip-flop, a second write flip-flop, a second read flip-flop, a write clock input, a write input, a not full output, first write logic gating means, second write logic gating means, a read clock input, a read input, a not empty output, first read logic gating means, and second read logic gating means.
The first write flip-flop generates a write pointer. The first read flip-flop generates a read pointer. The second write flip-flop receives as input the read pointer. The second read flip-flop receives as input the write pointer. The write clock input provides a write clock signal to the first write flip-flop and the second write flip-flop. The first write logic gating means is for generating the not full output from the write pointer and an output of the second write flip-flop. The second write logic gating means is for generating an input to the first write flip-flop from the write input and the not full output. The read clock input provides a read clock signal to the first read flip-flop and the second read flip-flop. The first read logic gating means is for generating the not empty output from the read pointer and an output of the second read flip-flop. The second read logic gating means is for generating an input to the first read flip-flop from the read input and the not empty output.
For example, the first write flip-flop is a toggle (T) flip-flop, the second write flip-flop is a delay (D) flip-flop, the first read flip-flop is a T flip-flop, and the second read flip-flop is a D flip-flop. In a preferred embodiment, the first write logic gating means includes a logic NOT gate which has an input connected to the output of the second write flip flop. The first write logic gating means also includes a first logic XOR means having a first input connected to an output of the logic NOT gate, a second input connected to the write pointer, and an output which generates the not full output. The first read logic gating means includes a first logic XOR gate having a first input connected to the output of the second read flip-flop, a second input connected to the read pointer, and an output which generates the not empty output. The second write logic gating means includes a first logic AND gate having a first input connected to the write input, a second input connected to the not full output, and an output connected to the input of the first write flip-flop. The second read logic gating means includes a second logic AND gate having a first input connected to the read input, a second input connected to the not empty output, and an output connected to the input of the first read flip-flop.
In a second preferred embodiment of the present invention, the one stage first-in-first-out synchronizer includes a first write flip-flop, a first read flip-flop, a second write flip-flop, a second read flip-flop, a third write flip-flop, a third read flip-flop, a write clock input, a write input, a not full output, first write logic gating means, second write logic gating means, a read clock input, a read input, a not empty output, first read logic gating means, and second read logic gating means.
The first write flip-flop generates a write pointer. The first read flip-flop generates a read pointer. The second write flip-flop receives as input the read pointer. The second read flip-flop receives as input the write pointer. The third write flip-flop has an input coupled to an output of the second write flip-flop. The third read flip-flop has an input coupled to an output of the second read flip-flop. The write clock input provides a write clock signal to the first write flip-flop, the second write flip-flop and the third write flip-flop. The first write logic gating means is for generating the not full output from the write pointer and an output of the third write flip-flop. The second write logic gating means is for generating an input to the first write flip-flop from the write input and the not full output. The read clock input provides a read clock signal to the first read flip-flop, the second read flip-flop and the third read flip-flop. The first read logic gating means is for generating

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