First-in, first-out memory with counter address pointers for gen

Details First-in, first-out memory with counter address pointers for gen First-in, first-out memory with counter address pointers for gen

1987-04-30

1989-09-05

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Serial read/write

365 78, 36523001, G11C 700, G11C 1900

Patent

active

048645435

ABSTRACT:
A first-in, first-out memory has a write pointer (34) that includes a higher-order ring counter (192) and a lower-order ring counter (190). Ring counters (190, 192) store respective higher-order and lower-order address digits that are together used to select one of a plurality of write select gates (202). Each gate (202) is operable to both power up and address is coupled to a respective memory word location. A read pointer (28) of the FIFO has an analogous architecture. The lower-order and higher-order address digits generated by the write and read pointers (34 and 28) are used by a pointer comparator (44) to generate a plurality of intermediate signals. The intermediate signals are in turn received by a flag decoder (52) that generates EMPTY, FULL, ALMOST-FULL/EMPTY, and HALF-FULL status flags. A write-read control section (48) of the FIFO has a pair of monostable multivibrators (68, 82) that generate write and read clock pulses of a uniform pulse width. The write/read control (48) further has a disabling circuit that disables either the read clock monostable multivibrator (82) or the write clock monostable multivibrator (68) responsive to an equality signal (50) from the flag decoder (52) and responsive whether the last pulse was a write clock or a read clock.

REFERENCES:
patent: 4314361 (1982-02-01), Jansen et al.
patent: 4592019 (1986-05-01), Huang et al.
patent: 4667313 (1987-05-01), Pinkham et al.
patent: 4694426 (1987-09-01), Mason
Computer Design, Aug. 1, 1986, pp. 109-112, "System Design/Memory Systems-FIFO RAM Controller" by Tom Pai.
Computer Design, Sep. 1, 1985, pp. 83-86, "High-Speed FIFO's Contend with Widely Differing Data Rates" by M. S. Miller et al.
Electronic Design Report, Jun. 11, 1987, pp. 77-86, "Rich with Logic, Memory ICs Hone Their Specialties".

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