First-in, first-out memory system having both simultaneous...

Details First-in, first-out memory system having both simultaneous... First-in, first-out memory system having both simultaneous...

2001-06-20

2004-08-17

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S053000

Reexamination Certificate

active

06779055

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to integrated circuits having memory system storage, and more specifically, to integrated circuits which utilize First-In, First-Out (FIFO) memory structures.
BACKGROUND OF THE INVENTION
In a real time debug system implemented on an integrated circuit data processing system, it is necessary to first store the debug messages before outputting the messages to a debugging tool. A first-in, first-out (FIFO) memory system is generally used to temporarily store the debug messages. Some of the messages may have multiple entries that need to be stored simultaneously and others need to be stored singly.
In order to store both kinds of messages in the same FIFO structure, a dual port FIFO may be used or separate, dedicated FIFOs may be used. However, a dual port FIFO requires a large surface area to implement because multiplexers are required on every entry of the FIFO to allow storage of both message types. Also, the large number of multiplexers requires a significant amount of logic to control the multiplexer select lines, with a corresponding increase in power consumption due to logic switching.
Another way to implement the FIFO memory system is to use two separate dedicated FIFOs. For example, one FIFO may receive only address information and the other FIFO may receive only data. This has the advantages of smaller surface area on an integrated circuit and less design complexity. However, it may lead to less efficient FIFO utilization when compared to the dual port FIFO because one of the FIFOs can become full and overflow while the other FIFO is not full.
Therefore, it would be desirable to have a FIFO memory system that makes efficient use of its storage area while also minimizing the control logic necessary to implement it.


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PCT International Search Report (PCT/US02/1455).

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