First-in first-out memory device

Details First-in first-out memory device First-in first-out memory device

1993-06-08

1994-12-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Serial read/write

365233, 365236, G11C 700

Patent

active

053750926

ABSTRACT:
In order to enable enlargement/reduction of data with a simple structure in a first-in first-out memory device thereby reducing the circuit scale of this device, output terminals (Q.sub.0 to Q.sub.3) of a read clock counter (16) are shifted to low order digits and connected to input terminals (A.sub.0 to A.sub.2) of a read address decoder (18). The read clock counter (16) and a read data sense amplifier (19) operate in response to read clocks (RK2). Enlarged read data (RD) are outputted from the read data sense amplifier (19). It is possible to implement enlargement/reduction of data by changing connection between the read clock counter (16) and the read address decoder (18), thereby remarkably simplifying the circuit structure of the first-in first-out memory device having an enlargement/reduction function.

REFERENCES:
patent: 4864543 (1989-09-01), Ward et al.
patent: 4985867 (1991-01-01), Ishii et al.

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