Static information storage and retrieval – Read/write circuit – Sipo/piso
Patent
1997-04-01
1999-05-04
Mai, Son
Static information storage and retrieval
Read/write circuit
Sipo/piso
365220, 365221, G11C 700
Patent
active
059011009
ABSTRACT:
An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.
REFERENCES:
patent: 4882710 (1989-11-01), Hashimoto
patent: 5029141 (1991-07-01), Yoshimoto
patent: 5570040 (1996-10-01), Lytle
patent: 5701267 (1997-12-01), Masuda
Kubida, Esq. William J.
Mai Son
Ramtron International Corporation
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