First-in, first-out integrated circuit memory device...

Details First-in, first-out integrated circuit memory device... First-in, first-out integrated circuit memory device...

2000-03-24

2001-01-09

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S220000, C365S221000, C365S189040, C365S230050, C345S519000

Reexamination Certificate

active

06172927

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, in general, to a first-in, first-out (“FIFO”) integrated circuit (“IC”) memory device. More particularly, the present invention relates to a FIFO memory device utilizing a dynamic random access memory (“DRAM”) memory array implemented in conjunction with enhanced dynamic random access memory technology (“EDRAM®” is a trademark of Enhanced Memory Systems, Inc.) in lieu of a conventional static random access memory (“SRAM”) based memory array.
FIFOs are integrated circuit (“IC”) devices which integrate a memory array, such as dual-ported SRAM memory array, with associated on-chip logic which may be utilized in a wide variety of data buffering applications such as graphics, disk controllers and communication networks. Despite requiring up to six transistors per memory cell as opposed to a single transistor and capacitor, SRAM memory has nevertheless been used in these applications due to its significant speed advantage over conventional dynamic random access memory (“DRAM”) due to the latter's inherent delays in bit line precharge, memory cell refresh, row access times and the like.
A FIFO memory's function allows quick write and read bursts to minimize the time spent by a central processing unit (“CPU”) when communicating with slower circuit elements thereby allowing the highest performance on the computer bus. FIFOs may also be used to enhance the throughput of time-critical systems developed for digital signal processing (“DSP”). Typical applications may involve allowing high speed throughput between DSPs in pipelined and parallel applications, supporting communications between a DSP and a host processor and buffering data between mismatched processor speeds and the buses. Typically, FIFO buffer memories allow the matching of multiple asynchronous systems whereby one system is operating at a significantly different clock frequency than another in order that data from one system may be temporarily stored before being read out for processing. Characteristically, the length of the FIFO is determined by the difference in clock rates and the amount of data to be buffered. When utilizing dual-ported SRAM, conventional FIFOs allow simultaneous access to the memory through two independent “write” and “read” ports. Since the data is always contiguous, an address bus is not needed and data is read out in the same order in which it was received.
In a synchronous FIFO, data may be clocked into and out of registers which buffer the actual memory array, so that shorter data setup and hold times are possible than with asynchronous FIFOs. Synchronous FIFOs also provide easier integration into synchronous systems. Writing and reading operations are controlled by “write” and “read” enables, while the “write” and “read” clocks may have either the same or different frequencies or have differing phase relationships.
In conventional FIFO design, four “flags” are provided to give the user information on the status of the memory array. In dual-ported RAM arrays, dedicated write and read address pointers are utilized, and the flag logic prevents illogical writes and reads from occurring. The “empty” flag indicates that the read and write cycle counts are equal, and will be automatically asserted after a reset, which functions to reset the cycle counters and returns both read and write pointers to memory address zero. The empty flag, therefore, prevents reading while empty, a data underflow condition. As a result, if the memory array is empty, a read cycle is inhibited until at least one data entry has been written.
On the other hand, a “full” flag indicates that the write and read counts are at a maximum distance apart, which implies that a full load of data has been written to the FIFO and has not yet been read out. The full flag, therefore, prevents writing while full, a data overflow condition. If the memory array is full, a write cycle is inhibited until at least one data entry has been read out. Once data that has been stored at a given address is read, it can then be overwritten. In such conventional FIFO operation, as long as the read pointer is advancing due to read cycles, the write pointer will “wrap around,” continuing past the last memory address and beginning again at the first memory address until the difference between the write and read counters indicate that the FIFO is full. Therefore, the flag status of the FIFO is a function of the difference between the pointers and not their absolute value. Resetting the FIFO simply initializes the address pointers to address zero.
The other pair of “flags” are conventionally known as programmable “almost empty” and programmable “almost full” flags which are user programmable to provide a preset offset before the empty and full conditions are reached to provide early warning to the user of approaching states of fullness or emptiness. In conventional FIFOs, multiple write enables and read enables are provided to be utilized at reset times to configure the FIFO for programmable flags.
To enable high speed device operation, conventional FIFOs have utilized SRAM memory arrays which are capable of reading and writing data more quickly than DRAM memory due, in part, to the fact that DRAM memory must be periodically refreshed, the bit lines precharged and the like. However, SRAM memory cells generally comprise four or even six transistors per memory cell as opposed to the single transistor and capacitor of the typical DRAM memory cell. As a consequence, SRAM memory cannot be as densely integrated as DRAM memory and is, therefore, more space consuming in terms of on-chip die area required to fabricate a comparable size memory array and consequently more costly to produce.
SUMMARY OF THE INVENTION
The EDRAM integrated circuit memory device architecture disclosed in the aforementioned United States Patent Applications is designed to minimize delays associated with row access, precharge and refresh operations of a conventional DRAM memory array. Essentially, this is accomplished through the integration of one or more relatively small SRAM row(s), or register(s), associated with the DRAM memory which allows reads to the device to be made only from the SRAM row(s) and, therefore, to be allowed to occur during refresh and precharge cycles of the DRAM array. Moreover, the SRAM row(s) and DRAM array are sufficiently decoupled so that writes to the device can occur to the DRAM (with a write-through to the SRAM if a row “hit” occurs) and reads and writes to the device can occur simultaneously. Alternatively, a common read/write path can be utilized to achieve a simplified architecture which provides the capability to hide DRAM precharge and refresh activities. The benefits of simultaneous read/writes versus a simplified common read/write path must be evaluated based on desired product price/performance positioning. As a consequence, utilizing EDRAM memory device technology, significantly smaller chip sizes can be achieved while maintaining the same number of array bits or much higher array density can be achieved while maintaining the same chip size. Both approaches yield an improved cost performance point.
Particularly disclosed herein is an integrated circuit FIFO memory device which comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one DRAM array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one or more SRAM row(s) interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array. Other embodiments where the SRAM rows have a width equal to a fraction and multiples of a row width are possible. The SRAM row(s) can be directly mapped to

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