First-in-first-out (FIFO) memory device for...

Details First-in-first-out (FIFO) memory device for... First-in-first-out (FIFO) memory device for...

1998-03-30

2002-08-27

Kim, Hong (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S201000

Reexamination Certificate

active

06442646

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a first-in first-out memory device for temporarily accumulating transfer data in a data processing apparatus and a data transfer apparatus.
2. Description of the Related Art
In a data processing apparatus and a data transfer apparatus such as a microprocessor, a microcomputer, a DSP, and a communication controller, a first-in first-out buffer memory for temporality accumulating transfer data is used. With a first-in first-out (hereinafter, referred to as “FIFO”) memory device, several configurations have been designed in the past. In the case where a data length of data to be written in a FIFO device is fixed, the FIFO device generally includes a shift register in which write unit registers are connected to each other. The circuit configuration and connecting wiring of the FIFO device using the shift register are simple. In the case where a data length of data to be written in a FIFO device is variable, the configuration of the FIFO device becomes complicated. In this case, the FIFO device is required to have a function of writing both data longer than a unit word length and data with a unit word length at a time.
In general, the support for the transfer of data with a plurality of word lengths is a function indispensable for a number of digital systems such as a computer. Therefore, a function of transferring data with a plurality of word lengths is also required of a FIFO device used in the digital system. Hereinafter, a conventional FIFO device having a function of transferring data with a plurality of word lengths will be described. The conventional FIFO described below is capable of transferring 1 byte, 2 bytes, and 4 bytes of data. The minimum unit to be written in the FIFO device is 1 byte. A transfer bus connected to the FIFO device is divided into a write bus and a read bus. The write bus is used for transferring data to be written in the FIFO device. The read bus is used for transferring data to be read from the FIFO device. The widths of the write bus and the read bus are respectively 4 bytes. As shown in Table 1, 1 byte of data, 2 bytes of data, and 4 bytes of data are arranged on a lower order side on the transfer bus. More specifically, the fourth byte is arranged on the highest order side and the first byte is arranged on the lowest order side.
TABLE 1
Arrangement of data on a transfer bus
Data
length/Byte
posi-
tion
4th byte
3rd byte
2nd byte
1st byte
1 byte of
—
—
—
B1
data
2 bytes
—
—
B2
B1
of data
4 bytes
B4
B3
B2
B1
of data
FIG. 3
shows a first exemplary configuration of a conventional FIFO device. A FIFO device
200
includes a shift register
203
, write enable control logics
204
, a shift-out selector
205
, an overflow/underflow detector
206
, a data top pointer
207
, and a data top pointer increasing/decreasing unit
208
. The FIFO device
200
is connected to a write data bus
201
and a read data bus
202
.
Hereinafter, an operation of the FIFO device
200
will be described with reference to FIG.
3
.
In the case where 1 byte of data is written in the FIFO device
200
, 1 byte of data is transferred to the shift register
203
using a lower order side of the write data bus
201
. One byte of data thus transferred is written in a 1-byte register
1
of the shift register
203
. Before 1 byte of data is written in the 1-byte register
1
, the entire shift register
203
is shifted up by 1 byte. More specifically, the write enable control logic
204
selects a central input, whereby each 1-byte register of the shifter register
203
receives data stored in the 1-byte register immediately below. When 1 byte of data is written in the FIFO device
200
, the data top pointer increasing/decreasing unit
208
adds one to a value of the data top pointer
207
.
In the case where 2 bytes of data are written in the FIFO device
200
, 2 bytes of data are transferred to the shift register
203
using a lower order side of the write data bus
201
. Two bytes of data thus transferred are written in 1-byte registers
1
and
2
of the shift register
203
. Before 2 bytes of data are written in the 1-byte registers
1
and
2
, the entire shift register
203
is shifted up by 2 bytes. More specifically, the write enable control logic
204
selects a left input, whereby each 1-byte register of the shifter register
203
receives data stored in two 1-byte registers below. When 2 bytes of data are written in the FIFO device
200
, the data top pointer increasing/decreasing unit
208
adds two to a value of the data top pointer
207
.
In the case where 4 bytes of data are written in the FIFO device
200
, 4 bytes of data are transferred to the shift register
203
using the entire write data bus
201
. Four bytes of data thus transferred are written in 1-byte registers
1
,
2
,
3
, and
4
of the shift register
203
. Before 4 bytes of data are written in the 1-byte registers
1
,
2
,
3
, and
4
, the entire shift register
203
is shifted up by 4 bytes. More specifically, the write enable control logic
204
selects a right input, whereby each 1-byte register of the shifter register
203
receives data stored in four 1-byte registers below. When 4 bytes of data are written in the FIFO device
200
, the data top pointer increasing/decreasing unit
208
adds four to a value of the data top pointer
207
.
In the case where data is read from the FIFO device
200
, 1-byte registers are selected by the shift-out selector
205
in accordance with the number of bytes to be read. The number of bytes to be read from the FIFO device
200
is 1, 2, or 4. The 1-byte register selected by the shift-out selector
205
is placed lower than a position designated by the data top pointer
207
. The data of the 1-byte register thus selected is transferred using a lower order side of the read data bus
202
. A value of the data top pointer
207
is decreased by 1, 2, or 4 in accordance with the number of bytes of read data.
In the case where a value of the data top pointer
207
exceeds 32 by writing data in the FIFO device
200
, the overflow/underflow detector
206
detects a FIFO overflow. In the case where a value of the data top pointer
207
becomes negative by reading data from the FIFO device
200
, the overflow/underflow detector
206
detects a FIFO underflow. During the FIFO over-flow/underflow detection, reading/writing of data with respect to the FIFO device
200
is limited.
As described above, reading/writing of 1, 2, or 4 bytes of data with respect to the FIFO device
200
is performed. In the FIFO device
200
, data with three different lengths is directly written in the shift register
203
, so that each byte register requires three shift paths and a selector for selecting either of the three paths. Herein, three shift paths refer to a path for shifting data to a register immediately above, a path for shifting data to two registers above, and a path for shifting data to four registers above. In the case where the FIFO device
200
is mounted on a chip, three shift paths and a selector are required of each byte register, so that the circuit area of the FIFO device on the chip increases.
FIG. 4
shows a second exemplary configuration of a conventional FIFO device. A FIFO device
300
includes a byte register
303
, write selectors
304
, a read selector
305
, an overflow/underflow detector
306
, a read pointer
307
, a read pointer increasing unit
308
, a write pointer
309
, a write pointer increasing unit
310
, and a write enable control logic
311
. The FIFO device
300
is connected to a write data bus
301
and a read data bus
302
.
Hereinafter, an operation of the FIFO device
300
will be described with reference to FIG.
4
.
In the case where data is written in the FIFO device
300
, data is transferred using the write data bus
301
. The data transferred from the write data bus
301
is input to all the write selectors
304
. The write selectors
304
are each provided for each 1-byte register. Only the write selector
304
corresponding to a 1-byte register to which d

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