First-In-First-Out (FIFO) memories having dual descriptors and c

Details First-In-First-Out (FIFO) memories having dual descriptors and c First-In-First-Out (FIFO) memories having dual descriptors and c

1997-05-30

2000-09-05

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 52, 711147, 711150, 711168, 711208, G06F 500, G06F 1206

Patent

active

061157619

ABSTRACT:
To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

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patent: 5794073 (1998-08-01), Ramakrishnan et al.

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