Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2001-02-08
2004-02-24
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S033000, C710S034000, C710S052000, C710S053000
Reexamination Certificate
active
06697889
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an FIFO (First-In First-Out) data transfer control device for controlling transfer, which is performed in a processor having a plurality of operation units for transferring an arbitrary number of data to an output device via a first-in first-out storage device in accordance with one instruction. This first-in first-out storage device will be simply referred to as an “FIFO” hereinafter. Particularly, the invention relates to an FIFO data transfer control device which can prevent overflow from the FIFO.
2. Description of the Background Art
In a processor or the like having a plurality of operation units, an FIFO is used for absorbing differences in processing timing with respect to an output device. Referring to
FIG. 22
, a processor
140
in the prior art includes a plurality of operation units
40
, an output FIFO data transfer control device
142
receiving the outputs of operation units
40
, and an output FIFO
44
which temporarily holds the output of output FIFO data transfer control device
142
, and then sends it to an output device
46
.
Output FIFO data transfer control device
142
includes an instruction analyzing portion
150
for analyzing a write instruction for output FIFO
44
, a data count portion
152
for counting the number of data written into output FIFO
44
, a check flag producing portion
154
for producing a flag to be used for determining whether output FIFO is “Full” or not, and a Full check portion
156
for determining whether output FIFO
44
is in the Full state based on the Full flag produced by check flag producing portion
154
.
Referring to
FIG. 23
, output FIFO data transfer control device
142
operates as follows. First, instruction analyzing portion
150
analyzes the write instruction sent from operation unit
40
for output FIFO
44
, and writes the data into output FIFO
44
in a step
1
(the “step” will be simply referred to as “S” in the following description). Data count portion
152
increments the count every time instruction analyzing portion
150
writes the data into output FIFO
44
(S
2
) so that the number of data written into output FIFO
44
is counted. Check flag producing portion
154
sets the check flag (fullcheck) when the count value of data count portion
152
is equal to or larger than the size of output FIFO
44
.
In output FIFO
44
, if it is impossible to write the data into a bank next to a bank into which data is being written, the flag of OFIFO_full_flag is set to indicate this fact. Full check portion
156
obtains a logical AND between OFIFO_full_flag and fullcheck. If the logical AND is equal to 1, Full check portion
156
determines that writing into FIFO
44
is impossible, and sets the value of flag fullcheck to 1 (S
3
). In this case, therefore, the check portion
156
suspends the write operation, which is to be performed for writing data into output FIFO
44
in accordance with the next instruction, until all the data in the next bank of output FIFO
44
is completely read out and thus the next bank becomes empty (i.e., until OFIFO_full_flag becomes equal to 0) (S
5
).
According to the conventional method described above, it is detected that data has been written into an end of a certain bank in output FIFO
44
, and therefore has reached the end of the bank. Thereafter, it is determined whether data can be written into the next bank. Thus, determination of whether data can be written into the next bank is performed after the data is written into the end of the bank preceding the next bank.
Therefore, the conventional method suffers from such a problem that the data writing cannot be stopped even when Full check portion
156
determines that the writing to the next bank is impossible, if the data must be stored into two or more banks in accordance with one data transfer instruction.
For overcoming the above problem, it is necessary on the side of program, which is to be executed by the processor, to check the Full state of output FIFO
44
without fail before performing the processing of writing the data into output FIFO
44
. If the output FIFO data transfer control device in the prior art is used for this check processing, the data processing transfer speed is lowered.
Referring to
FIG. 24
, it is assumed that output FIFO
44
has a four-bank structure. As shown in
FIG. 24
, it is also assumed that a free space corresponding to one data is present in an end of bank
2
, and bank
3
is already written entirely. In the conventional method, the FULL check is performed at the time when the last data is written in bank
2
. Therefore, overwriting occurs, for example, if the instruction for writing the last data in the bank
2
requests the transfer of two or more (e.g., three) data. More specifically, the overwriting occurs in spite of the fact that the two data in bank
3
are not yet read out.
For preventing the above problem, it is necessary on the program side to check whether output FIFO
44
is in the Full state before the transfer, as already described. In some cases, this check must be performed every time the instruction is issued.
A proposal for overcoming the above problem is disclosed in Japanese Patent Laying-Open No. 11-161467. According to the prior art disclosed in this publication, a memory is divided by an appropriate boundary into two blocks, which are used as different FIFOs, respectively. A method of calculating the next write position of each FIFO (i.e., determining the next address) is devised so as to prevent complication of a circuit structure of a write/read control circuit. Also, a comparison between the size of next data to be written and the free space is made in each FIFO, and it is determined for each FIFO whether the free space is insufficient or not, and whether the writing can be performed or not.
In this prior art, the number of FIFOs is restricted to two, and therefore data of a large capacity cannot be handled. Since the two blocks are used as different FIFOs, respectively, the utilization efficiency of the memory region is low.
Japanese Patent Laying-Open No. 63-167949 has disclosed a data transfer system, which is formed of a plurality of FIFOs connected in series, and can achieve a high efficiency. According to this system, information indicating whether an FIFO buffer is empty or not is available for each FIFO, and thereby an extent or degree of a total free space in the FIFOs is determined. The size of the free space thus determined is compared with the size of the transfer data, and the data is written into the FIFO buffer only when the free space is larger than the data.
In this prior art, information indicating whether the FIFO is empty or not is obtained for each FIFO, and it is determined that each FIFO is not empty when even one data is written into the same FIFO. Accordingly, even if the FIFO actually has a free space, this free space cannot be used in some cases. Therefore, the whole region of the FIFO cannot be used efficiently so that the transfer efficiency likewise becomes low.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide an FIFO data transfer control device, in which management or control of a free space in an FIFO by a program is not required, and therefore a data transfer processing speed can be increased.
Another object of the invention is to provide an FIFO data transfer control device, in which management or control of a free space in an FIFO by a program is not required, and an FIFO region can be efficiently used so that a data transfer processing speed can be increased.
Yet another object of the invention is to provide an FIFO data transfer control device, in which management or control of a free space in an FIFO by a program is not required, and the free space of the FIFO can be efficiently utilized in accordance with an amount of data to be processed by a program to be executed so that a data transfer processing speed can be increased.
According to the invention, an FIFO data transfer control device includes an in
Inoue Yoshitsugu
Kawai Hiroyuki
Kobara Junko
Streitenberger Robert
Gaffin Jeffrey
McDermott & Will & Emery
Peyton Tammara
Renesas Technology Corp.
LandOfFree
First-in first-out data transfer control device having a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with First-in first-out data transfer control device having a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and First-in first-out data transfer control device having a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3322693