First-in first-out buffer memory with improved status flags

Details First-in first-out buffer memory with improved status flags First-in first-out buffer memory with improved status flags

1988-06-15

1989-12-19

Heinz, A. J.

Static information storage and retrieval

Read/write circuit

Serial read/write

365 78, 36518905, G11C 700, G11C 1900

Patent

active

048887390

ABSTRACT:
A first-in first-out buffer memory with improved status flags to indicate not only memory empty and memory full conditions, but to further indicate conditions such as almost empty, almost full and half-full is disclosed. To generate the flags, counters continuously count the number of write and read operations, with a subtractor coupled thereto providing as an output the difference between the two counts. Time delay circuits initiated by write or read operations provide time delays sufficient to enable the counters and the subtractor to settle before clocking the result into a latch. The output of the latch is decoded, with a further time delay circuit clocking the decoder output thereinto to provide output signals for the foregoing status flags. The use of the time delay circuits and the clocking of status flags avoids any significant flag invalid time, making the flag signals constantly monitorable without regard to the timing of read and write operations.

REFERENCES:
patent: 4694426 (1987-09-01), Mason
Computer Design, Aug. 1, 1986, pp. 109-112, "FIFO RAM Controller Tackles Deep Data Buffering", by Tom Pai.
"FIFO-The Glue Holding Systems Together", by Ching-Lin Jiang and Michael Bolan, pp. 181-189, Computer Design Magazine, Jun. 1983.

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