First-in-first-out buffer memory

Details First-in-first-out buffer memory First-in-first-out buffer memory

1995-07-06

1996-12-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Parallel read/write

365221, 36518907, 36523005, 365236, G11C 700

Patent

active

055879535

ABSTRACT:
Disclosed is the FIFO buffer memory, comprising a core memory 12 having a dual port structure, for substantially storing data, first and second address decoders 13 and 14 responsive to read and write clock signals, for producing addresses indicative of directing locations in the core memory when data is written in the core memory or when the data is read from the core memory, and a status detector 15 for generating memory status signals indicating whether the data can be written in the FIFO buffer memory or whether the data can be read from the FIFO buffer memory, i.e. full and empty flags. The buffer memory can be embodied without use of complicated circuits such as address counter, address register and comparator, which can be operated at high speed and embodied with high-density integration.

REFERENCES:
patent: 5426612 (1995-06-01), Ichige et al.

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