Firmware/hardware system for testing interface logic of a data p

Details Firmware/hardware system for testing interface logic of a data p Firmware/hardware system for testing interface logic of a data p

1977-08-04

1979-06-26

Nusbaum, Mark E.

Boots, shoes, and leggings

235302, G06F 1100

Patent

active

041595343

ABSTRACT:
A firmware/hardware method and system is provided for testing interface logic in a data processing system having a plurality of system units intercommunicating over a common electrical bus. Under firmware control, an incorrect parity is generated in a main memory address to be loaded into output registers of a system unit supplying information to the bus. A bus cycle request is issued by the system unit, and when the bus is made available the system unit acknowledges the memory address to initiate a transfer of data from the bus into the input registers of the system unit. Thereafter, the data in the output registers of the device may be compared with the data in the input registers to detect interface logic errors.

REFERENCES:
patent: 3576541 (1971-04-01), Kwan et al.
patent: 3579199 (1971-05-01), Anderson et al.
patent: 4048481 (1977-09-01), Bailey, Jr. et al.

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