Firmware algorithm for initializing memory modules for...

Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration

Reexamination Certificate

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C711S167000

Reexamination Certificate

active

07096349

ABSTRACT:
A technique for initializing a memory controller of a plurality of memory modules for optimum system performance is presented. A plurality of optimum sets of operational parameters that are supported by the memory controller and the plurality of memory modules are determined. A plurality of benchmark calculations using the plurality of optimum sets of operational parameters produces a plurality of benchmark numbers. The memory controller is configured with the one of the plurality of optimum sets of operational parameters that produces the best of the plurality of benchmark numbers. The benchmark calculations can be based on a variety of conditions, for example, burst length or the minimum time to read a random row of memory. Additionally, the benchmark calculations can be weighted in favor of frequency.

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JEDEC Solid State Technology Association “Double Data Rate (DDR) SDRAM Specification”, Release 2, May 2002, pp. 1-75.

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