Finned memory cells

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S315000, C257SE21014, C257SE27091, C257SE27096, C438S211000, C438S257000

Reexamination Certificate

active

07968930

ABSTRACT:
For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching.

REFERENCES:
patent: 7026195 (2006-04-01), Cheng et al.
patent: 7297600 (2007-11-01), Oh et al.
patent: 7473611 (2009-01-01), Cho et al.
patent: 2006/0141706 (2006-06-01), Hong
patent: 2007/0090443 (2007-04-01), Choi et al.
patent: 2008/0009115 (2008-01-01), Willer et al.

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