Boots – shoes – and leggings
Patent
1992-12-15
1993-12-21
Mai, Tan V.
Boots, shoes, and leggings
G06F 700
Patent
active
052726614
ABSTRACT:
A finite field parallel multiplier in GF(q.sup.m) including a router for directing 2m-1 components in m groups of m single-component signal lines towards m computing circuits for performing multiply and add modulo-q. The router guides m components from a first finite field element along with an additional m-1 components generated from linear combinations of the m components of the first finite field element. Each of the computing circuits receives all of the components from the second finite field element and m components provided by one set of signal lines through the router. Each computing circuit generates a single component for the resultant finite field element. These resulting components may be input through a basis change circuit to obtain a result in the desired basis.
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C. C. Wang et al., "VLSI Architectures for Computing Multiplications and Inverses in GF (2.sup.M)." IEEE Trans. on Computers, vol. C-34, No. 8, pp. 709-717, Aug. 1985.
M. Morii et al., "Efficient Bit-Serial Multiplication and the Discrete-Time Wiener-Hopf Equation Over Finite Fields." IEEE Trnas. on Inform. Theory, vol. 35, No. 6, pp. 1177-1183, Nov. 1989.
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P. A. Scott et al., "A Fast VLSI Multiplier for GF (2.sup.M)." IEEE Journal on Selected Areas in Communications, vol. Sac-4, No. 1, pp. 62-65, Jan. 1986, plus additional 7 pages.
Esserman James N.
Gurantz Itzhak
Hebron Yoav
Raghavan Sreenivasa A.
Asher Robert M.
Comstream Corporation
Mai Tan V.
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