Redesign of sequential circuits to reduce clock period

Details Redesign of sequential circuits to reduce clock period Redesign of sequential circuits to reduce clock period

1996-04-29

1997-09-02

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364491, G06F 1750

Patent

active

056638884

ABSTRACT:
A process for redesign of a sequential circuit to provide a functionally equivalent circuit that can operate with a shorter clock cycle. It includes forming a path graph of the circuit, classifying short and long arcs of the graph and developing sets of short and long path inequalities from which there is developed an objective function which is solved to provide an optimal set of delay constraints. These are used to synthesize a new circuit which after retiming results in the desired redesigned circuit.

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