FinFET SRAM with asymmetric gate and method of manufacture...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S347000, C257SE27098, C438S286000

Reexamination Certificate

active

07737501

ABSTRACT:
A FinFET SRAM transistor device includes transistors formed on fins with each transistor including a semiconductor channel region within a fin plus a source region and a drain region extending within the fin from opposite sides of the channel region with fin sidewalls having a gate dielectric formed thereon. Bilateral transistor gates extend from the gate dielectric. An asymmetrically doped FinFET transistor has source/drain regions doped with a first dopant type, but the asymmetrically doped FinFET transistor include at least one of the bilateral transistor gate electrode regions on one side of at least one of the fins counterdoped with respect to the first dopant type. The finFET transistors are connected in a six transistor SRAM circuit including two PFET pull-up transistors, two NFET pull down transistors and two NFET passgate transistors.

REFERENCES:
patent: 6706571 (2004-03-01), Yu et al.
patent: 6909147 (2005-06-01), Aller et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2003/0201458 (2003-10-01), Clark et al.
patent: 2004/0099885 (2004-05-01), Yeo et al.
patent: 2004/0222477 (2004-11-01), Aller et al.
patent: 2006/0065831 (2006-03-01), Fukuyama et al.
patent: 2006/0091463 (2006-05-01), Donze et al.
patent: 2007/0257277 (2007-11-01), Takeda et al.
patent: 2008/0308850 (2008-12-01), Berthold et al.
Yang et al., “Fully Working 1.25μm2 6T-SRAM Cell with 45nm Gate Length Triple Gate Transistors,” IEDM Tech. Dig., 2003, pp. 23-26.

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