FinFET device with reduced DIBL

Details FinFET device with reduced DIBL FinFET device with reduced DIBL

2007-06-26

2007-06-26

Lindsay, Jr., Walter (Department: 2812)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S542000, C438S558000, C438S563000, C438S197000, C438S289000, C257SE21703

Reexamination Certificate

active

11201038

ABSTRACT:
FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing the same. The methods involve dopant implants into the insulator layer, thereby creating borophosphosilicate glass (BPSG) diffusion sources within the insulation layer underlying the active regions of the SOI wafer. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the active regions, thereby forming a retrograde dopant profile extending towards the channel region. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

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