FinFET device with reduced DIBL

Details FinFET device with reduced DIBL FinFET device with reduced DIBL

2006-03-07

2006-03-07

Lindsay, Jr., Walter L. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S351000, C257S369000

Reexamination Certificate

active

07009250

ABSTRACT:
FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing the same. The methods involve dopant implants into the insulator layer, thereby creating borophosphosilicate glass (BPSG) diffusion sources within the insulation layer underlying the active regions of the SOI wafer. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the active regions, thereby forming a retrograde dopant profile extending towards the channel region. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

REFERENCES:
patent: 4199773 (1980-04-01), Goodman et al.
patent: 5024965 (1991-06-01), Chang et al.
patent: 5112766 (1992-05-01), Fujii et al.
patent: 5164805 (1992-11-01), Lee
patent: 5166765 (1992-11-01), Lee et al.
patent: 5231045 (1993-07-01), Miura et al.
patent: 5315144 (1994-05-01), Cherne
patent: 5501993 (1996-03-01), Borland
patent: 5528063 (1996-06-01), Blanchard
patent: 5599728 (1997-02-01), Hu et al.
patent: 5614433 (1997-03-01), Mandelman
patent: 5930630 (1999-07-01), Hshieh et al.
patent: 5942781 (1999-08-01), Burr et al.
patent: 5960275 (1999-09-01), So et al.
patent: 6037617 (2000-03-01), Kumagai
patent: 6268630 (2001-07-01), Schwank et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6503783 (2003-01-01), Mouli
patent: 6635928 (2003-10-01), Mouli
patent: 6716682 (2004-04-01), Mouli
patent: 6872640 (2005-03-01), Mouli
patent: 6885055 (2005-04-01), Lee
patent: 6905918 (2005-06-01), Mouli
patent: 2002/0089032 (2002-07-01), Huang
patent: 2004/0197975 (2004-10-01), Krivokapic et al.
patent: 2004/0262688 (2004-12-01), Nowak et al.
patent: 2005/0017377 (2005-01-01), Joshi et al.
patent: 2005/0062088 (2005-03-01), Houston
patent: 2005/0077574 (2005-04-01), Mouli
patent: 2005/0087811 (2005-04-01), Liao et al.
patent: 2005/0093067 (2005-05-01), Yeo et al.
patent: 2005/0104130 (2005-05-01), Nowak et al.
patent: 2005/0145938 (2005-07-01), Lin
Park et al., “Dopant Redistribution in SOI during RTA: A Study on Doping in Scaled-down Si Layers”,IEEE, 1999, pp 14.2.1 through 14.2.4.
“A.1.3.2 Spurious Effects in Sub-Micron MOSFET2”, http://www.iue.tuwien.ac.at/diss/schrom/diss
ode90.html.
“2.7.2 Threshold Control”, http://www.iue.tuwien.ac.at/diss/schrom/diss
ode26.html.
“Random discrete dopant fluctuation; Ultra-thin channel SOI”, http://www.research.ibm.com/0.1um/pwong.html.

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