Fine resolution digital delay line with coarse and fine adjustme

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

375376, 370517, 370519, 331 25, H03D 324

Patent

active

058449540

ABSTRACT:
A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.

REFERENCES:
patent: 5109394 (1992-04-01), Hjerpe et al.

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