Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-10-26
2002-04-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S614000, C228S180220
Reexamination Certificate
active
06372622
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to surface-mount semiconductor device processing, and, more particularly, to solder bump formation on semiconductor devices and products.
DESCRIPTION OF THE RELATED ART
Electronic assemblies often employ integrated circuit (IC) devices, which are generally characterized as being electrically and mechanically attached to a substrate of an electronic circuit assembly with a number of terminals or leads that are soldered, such as with a tin-lead solder, to conductors on the surface of the substrate. A prominent example of a SM IC is a flip chip, which has terminals typically in the form of solder bumps. Due to the numerous functions typically performed by the microcircuitry of a flip chip, a relatively large number of solder bumps are often required.
As integrated circuit sizes continue to shrink, there is an increased need for fine pitch solder bump flip chip assemblies in order to provide enhanced electrical performance together with reduced cost. However, existing solder bump technology provides insufficient solder volume to ensure reliable performance for devices with less than a 225 um pitch. Pitch is defined as the minimum center-to-center distance between solder bumps on a particular flip chip assembly. Moreover, because existing electroplate bump technology uses a single photo exposure to define the openings for both the conductive stud and solder bump plating, the plated solder volume is limited by both diameter and circular shape of the conductive stud.
FIG. 1
, labeled prior art, illustrates in cross-section a portion of a semiconductor device
13
that has been partially fabricated using a single photo exposure step to define the openings for both a copper stud and solder bump plating. Semiconductor device
13
includes substrate
10
, bond pads
12
, passivation layer
11
, barrier layer
14
, photoresist
16
, plated copper studs
18
, and plated solder bumps
17
and
19
. As shown in
FIG. 1
, plated solder bumps
17
and
19
have been grown from copper studs
18
and mushroomed over photoresist layer
16
. That is, plated solder bumps
17
and
19
overflow edges
21
. When the existing technology is used for fine pitch application, plated solder bumps
17
and
19
encroach upon each other, as shown in
FIG. 1
, possibly shorting bond pads
12
. Furthermore, as pitch decreases, the volume of solder bumps
17
and
19
also typically decreases to prevent such a shorted condition. Reduced solder volume causes lessened standoff between surface-mount coupled devices which results in the inability of underfill material to flow between the coupled devices. Both reduced standoff and insufficient underfill flow could result in lessened reliability.
REFERENCES:
patent: 5989993 (1999-11-01), Zakel et al.
Beddingfield Stanley Craig
Mitchell Douglas G.
Tan Qing
Chiu Joanna G.
Motorola Inc.
Niebling John F.
Zarneke David A.
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