Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2007-02-28
2009-08-18
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S117000, C710S243000
Reexamination Certificate
active
07577780
ABSTRACT:
A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.
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Design and Implementation of a Lottery-Based Bandwidth Guaranteed and Low Latency Arbiter for On-Chip Bus, Yao et al., Jul. 2006 (publication date indicated in Bandwidth Issues White Papers at silicon.com).
Bandwidth Issues White Papers, <http://whitepapers.silicon.com/0,39024759,60402988p,00.htm>, accessed on Oct. 23, 2008.
Huang Juinn-Dar
Jou Jing-Yang
Lee Geeng-Wei
Lin Bu-Ching
Birch & Stewart Kolasch & Birch, LLP
Dang Khanh
National Chiao Tung University
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