Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-30
2001-10-09
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C326S039000, C326S041000, C326S047000
Reexamination Certificate
active
06301696
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to programmable logic devices, and more particularly, to a method and apparatus for increasing the speed of such devices.
2. Description of the Related Art
An excellent discussion of programmable logic devices (PLDs) can be found in Chapter Two of the textbook entitled “Computer Architecture and Organization” by John P. Hayes (McGraw-Hill, 3rd Edition, 1998). As stated therein, PLDs are integrated circuits (ICs) that contain many gates or other general-purpose cells whose interconnections can be configured or “programmed” to implement any desired combinational or sequential function. Two techniques are used to program PLDs: mask programming, which requires a few special steps in the IC chip-manufacturing process, and field programming, which is done by designers or end users “in the field” via small, low-cost programming units. Some field-programmable PLDs are erasable, implying that the same IC can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product.
The connections leading to and from logic elements in a PLD contain transistor switches that can be programmed to be switched on or switched off. These switches are laid out in two-dimensional arrays so that large gates can be implemented with minimum IC area. These arrays of switches are known as programmable logic arrays (PLAs).
A field-programmable gate array (FPGA) is a two-dimensional array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types are not restricted to gates. The cell types may be small multifunction circuits (or configurable functional blocks) capable of realizing all Boolean functions of a few variables. For example, configurable functional blocks typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain one or two flip-flops. Two types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Like all field programmable devices, FPGAs are suitable for implementing prototype designs and for small-scale manufacture.
FPGAs can store the program that determines the circuit to be implemented in a RAM or PROM on the FPGA chip. The pattern of the data in this configuration memory CM determines the cells' functions and their interconnection wiring. Each bit of CM controls a transistor switch in the target circuit that can select some cell function or make (or break) some connection. By replacing the contents of CM, designers can make design changes or correct design errors. The CM can be downloaded from an external source or stored on-chip. This type of FPGA can be reprogrammed repeatedly, which significantly reduces development and manufacturing costs. Some FPGAs employ fuses or antifuses as switches, which means that each FPGA IC can be programed only once. These one-time programmable FPGAs have other advantages, however, such as higher density, and smaller or more predictable delays.
Thus, as can be gathered from Mr. Hayes' textbook, PLDs and FPGAs are flexible devices that can be configured to implement many different functions.
Examining FPGAs in more detail, there is typically included a physical template that includes an array of circuits, sets of uncommitted routing interconnects, and sets of user programmable switches associated with both the circuits and the routing interconnects. Thus, an FPGA includes many programmable switches or connections that include programmable interconnections or routing interconnects of the FPGA array, as well as switches or connections within circuits or devices included within the FPGA. When these switches are properly programmed (set to on or off states), the template or the underlying circuit and interconnect of the FPGA is customized or configured to perform specific customized functions. By reprogramming the on-off states of these switches, an FPGA can perform many different functions. Thus, the ability to program these switches provides for a very flexible device.
These switches can be implemented in various technologies, such as ONO antifuse, M—M antifuse, SRAM memory cell, Flash EPROM memory cell, and EEPROM memory cell. In a memory cell controlled switch implementation, an NMOS transistor is typically used as the switch to either connect or disconnect two selected points (A, B) in the circuit. The NMOS' source and drain nodes are connected to points A, B respectively, and its gate node is directly or indirectly connected to the memory cell. By setting the state of the memory cell to either logical “1” or “0”, the switch can be turned on or off and thus point A and B are either connected or disconnected.
Referring to
FIG. 1
, there is illustrated an FPGA
20
and an application specific integrated circuit (ASIC)
22
. Assume that the FPGA
20
has been configured to perform one specific function, and assume that the ASIC
22
has been designed and manufactured to perform that same specific function. Because the FPGA
20
is a very flexible device that is capable of implementing many different functions, it is necessarily a larger device than the ASIC
22
. This is because the FPGA
20
, as a flexible device, includes a large amount of excess circuitry that is not being used to perform the one specific function and that excess circuitry has been eliminated in the design of the ASIC
22
. Furthermore., the FPGA
20
is most likely a slower device and consumes more power than the ASIC
22
. This is because many of the circuit connections within the FPGA
20
are provided by transistors, whereas those same circuit connections in the ASIC
22
are hard-wired connections. The transistor connections, even when the transistors are turned on, provides more resistance than a hard-wired connection. This results in slower speed with greater power consumption. The ASIC
22
, on the other hand, is not a flexible device. In other words, once the ASIC
22
has been designed and manufactured it cannot be reconfigured to perform a different function like the FPGA
20
can.
Once a specific configuration for the FPGA
20
(or other PLD) has been decided upon, it would appear that replacing the FPGA
20
with the ASIC
22
would be the most efficient thing to do. But even though the ASIC
22
provides a smaller and faster implementation of the one specific function than the FPGA
20
, the manufacture of the ASIC
22
requires the circuitry to be substantially redesigned. This redesigning becomes substantially more complex if the ASIC
22
is to be embedded in a larger IC. Such redesigning takes time and resources to perform, and consequently, slows down the manufacturing process and increases the cost of the device.
Thus, once a specific configuration of an FPGA (or other PLD) has been decided upon, there is a need for a way to improve the performance (e.g., speed, power consumption, clock skew) of the FPGA that does not involve substantially redesigning the chip.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a method of making an integrated circuit (IC). The method includes establishing an initial design for a programmable logic device (PLD) to be included in the IC that includes programmable connections that can be programmed to implement a desired function; establishing an underlying physical template for the IC wherein at least a portion of the template is based on the initial design for the PLD; selecting a specific configuration of the programmable connections in the PLD; performing a manufacturing process of the IC using the underlying physical template; and, during the manufacturing process of the IC, bypassing selected on-state transistors in the PLD used to implement the specific configuration of the programmable connections with metal connections while conservi
Feng Sheng
Huang Eddy Chieh
Lien Jung-Cheun
Sun Chung-yuan
Actel Corporation
McCutchen Doyle Brown & Enersen LLP
Smith Matthew
Speight Jibreel
LandOfFree
Final design method of a programmable logic device that is... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Final design method of a programmable logic device that is..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Final design method of a programmable logic device that is... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2574215