Fin-type semiconductor device with low contact resistance

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S350000, C257SE29151

Reexamination Certificate

active

11123145

ABSTRACT:
A semiconductor device comprises a fin-type semiconductor region (fin) on a support substrate, having a pair of generally vertical side walls and an upper surface coupling the side walls; an insulated gate electrode structure traversing an intermediate portion of the fin and having side walls in conformity with the side walls of the fin; source/drain regions formed in the fin on both sides of the gate electrode; side wall insulating films including a first portion formed on the side walls of the conductive gate electrode and a second portion formed on the side walls of the fin and having an opening in the source/drain regions extending from an upper edge to a lower edge of each of the side walls; a silicide layer formed on each surface of the source/drain regions exposed in the opening of the second side wall insulating film; and source/drain electrodes contacting the silicide layers.

REFERENCES:
patent: 6693046 (2004-02-01), Takigawa et al.
patent: 6707156 (2004-03-01), Suzuki et al.
patent: 6835609 (2004-12-01), Lee et al.
patent: 7105894 (2006-09-01), Yeo et al.
patent: 7115945 (2006-10-01), Lee et al.
patent: 2002-26299 (2002-01-01), None
patent: 2002-289871 (2002-10-01), None
Fu-Liang Yang et al., 35nm CMOS FinFETs, 2002 Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2002.
Bin Yu et al., FinFET Scaling to 10nm Gate Length, Department of EECS, University of California, Berkeley, CA, IEEE, 2002.

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