Fin field effect transistors having multi-layer fin patterns

Details Fin field effect transistors having multi-layer fin patterns Fin field effect transistors having multi-layer fin patterns

2008-01-29

2008-01-29

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

C257S368000, C257SE29193

Reexamination Certificate

active

07323710

ABSTRACT:
A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.

REFERENCES:
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patent: 6635989 (2003-10-01), Nilsson et al.
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