Fin field effect transistor with self-aligned gate

Details Fin field effect transistor with self-aligned gate Fin field effect transistor with self-aligned gate

2001-09-27

2004-02-10

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S159000, C438S163000, C438S206000, C438S242000, C438S279000, C438S283000, C257S302000

Reexamination Certificate

active

06689650

ABSTRACT:

DESCRIPTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a method of forming a metal oxide semiconductor field effect transistor (MOSFET) comprising thin vertical channels (i.e., the FIN) controlled by a double-gate, which involves using a trough to define the channel regions as well as the damascene gate, so as to provide a self-aligned gate. The present invention also relates to a sub-0.05 &mgr;m double-gated/double-channel FIN MOSFET structure wherein the gate is self-aligned to the channel regions as well as the source/drain junctions.
2. Background of the Invention
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage V
t
in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al., “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992, have shown that to reduce short-channel effects for sub-0.05 &mgr;m MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of the prior art MOSFETs consists of a very thin vertical Si layer (FIN) for the channel, with two gates, one on each side of the channel. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
FIN MOSFETs offer potential benefits in performance as compared with conventional MOSFETs; See, for example, X. Huang, et al., IEDM Tech. Dig. 1999, p.67. However, in prior art FIN MOSFETs, the gate conductor is not self-aligned to the source/drain diffusion junctions or the channel regions. Therefore, there will be a large series resistance between the channel and the heavily doped source/drain diffusion junctions.
To date, there are no adequate means for fabricating double-gated FIN MOSFET structures in which the gate is self-aligned to the source/drain diffusion junctions and the channels. Thus, there is a continued need for developing a new and improved method of fabricating double-gated FIN MOSFETs in which such self-alignment between the gate and the source/drain diffusion junctions and channels is achieved.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a double-gated/double-channel FIN MOSFET structure that has sub-0.05 &mgr;m channel lengths associated therewith.
Another object of the present invention is to provide a FIN MOSFET structure that has excellent short-channel characteristics.
A further object of the present invention is to provide a FIN MOSFET structure in which the variation in threshold voltage with drain voltage and with the gate length is substantially less than that of a singled-gated MOSFET structure of the same channel length.
A yet further object of the present invention is to provide a FIN MOSFET structure which has double the on-current as compared with conventional single-gated structures of the same channel length.
A still further object of the present invention is to provide a FIN MOSFET structure in which the gate is self-aligned to the source/drain diffusion junctions and channel regions thereby significantly reducing the series resistance between the channels and the heavily doped source/drain diffusion junctions.
These and other objects and advantages are achieved in the present invention by utilizing a method wherein a trough is employed, not only to define the regions where the channels are formed, but also to form a damascene gate. Such a method allows for the formation of a double-gated/double-channel FIN MOSFET structure in which the gate is self-aligned to the channel regions and the source/drain diffusion junctions.
One aspect of the present invention thus relates to a method of fabricating a double-gated/double-channel FIN MOSFET structure having a gate region that is self-aligned with the source/drain diffusion junctions and channel regions. Specifically, the method of the present invention comprises the steps of:
(a) forming at least one patterned region atop a surface of an insulating region, said at least one patterned region comprising a Si-containing layer present atop said insulating region, a pad oxide present atop said Si-containing layer and a polish stop layer present atop said pad oxide;
(b) forming planarizing insulating regions abutting each patterned region, said planarizing insulating regions are formed on exposed portions of said insulating region, said planarizing insulating region being co-planar with a top surface of said polish stop layer;
(c) forming a hardmask on a portion of said at least one patterned region, said hardmask being used to define channel regions in said at least one patterned region;
(d) selectively removing a portion of said hardmask, said polish stop layer and said pad oxide layer so as to expose a portion of said Si-containing layer thereby forming channels regions and a trough;
(e) forming a gate region in said trough; and
(f) removing said polish stop layer and said pad oxide abutting said gate region so as to expose portions of said Si-containing layer and forming source/drain diffusion regions therein.
Another aspect of the present invention relates to a double-gated/double-channel FIN MOSFET structure which is formed utilizing the method of the present invention. Specifically, the inventive double-gated/double-channel FIN MOSFET comprises:
a bottom Si-containing layer;
an insulating region present atop said bottom Si-containing layer, said insulating region having at least one partial opening therein;
a gate region formed in said at least one partial opening, said gate region comprising two regions of gate conductor that are separated from channel regions by an insulating film, said insulating film having opposite vertical surfaces adjacent to the channel regions;
source/drain diffusion regions abutting said gate region, said source/drain diffusion regions having junctions that are self-aligned to the channels regions as well as the gate region; and
insulating spacers that separate the gate region and the source/drain diffusion regions formed orthogonal to said insulating film.


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Chang, L., “Industrial Planar FinFET Fabrication Using Standard Processing Tools,” (last modified Feb. 21, 2001), p. 1, <http://hera.berkeley.edu/IRO/Summary/01abstracts/leland.2.html>.
Choi, Y., et al., “Asymmetrical Double Gate FinFET,” (last modified Feb. 21, 2001) p.1, <http://buffy.eecs.berkeley.edu/IRO/Summary/00abstr

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