Fin field effect transistor and method for manufacturing fin...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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C438S299000, C257S412000, C257SE21439

Reexamination Certificate

active

07319063

ABSTRACT:
The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.

REFERENCES:
patent: 6376320 (2002-04-01), Yu
patent: 6929992 (2005-08-01), Djomehri et al.
patent: 2003/0008487 (2003-01-01), Iwai
patent: 2004/0061191 (2004-04-01), Paton et al.
patent: 2006/0011996 (2006-01-01), Wu et al.

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