Filtering method for digital phase lock loop

Details Filtering method for digital phase lock loop Filtering method for digital phase lock loop

2002-07-26

2004-11-16

Tse, Young T. (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S372000

Reexamination Certificate

active

06819730

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to digital phase lock loop technology, and more particularly, to a filtering method used in digital phase lock loop.
BACKGROUND OF THE INVENTION
Phase lock loop (PLL) is a closed loop tracking system which can track the phase and frequency of an input signal. When PLL tracks an input signal with constant frequency, there is no frequency difference. When PLL tracks an input signal with variable frequency, the tracking accuracy is very high.
There are two kinds of PLL: analog phase lock loop (APLL) and digital phase lock loop (DPLL). An APLL circuit consists of a phase detector (PD), a loop filter (LF) and a voltage-controlled oscillator (VCO). APLL has better vibration suppression performance, but has discreteness in technology, a higher manufacture cost and lower stability.
If a portion of a DPLL circuit comprises a digital circuit, it is generally referred to as a partial DPLL. The principle is similar to APLL, and as its frequency control still applies, some disadvantages, such as high discreteness, high manufacture difficulty and high cost, exist. DPPL consists of all digital circuits. A newer implementation method of DPPL is proposed by U.S. Pat. No. 5,033,064. The DPPL implemented by this method has better vibration transfer characteristics and net vibration output characteristics, but there is no effective loop filtering method and vibration filter performance at lower band frequencies is not ideal.
SUMMARY OF THE INVENTION
The present invention provides a filtering method for DPLL (DPLL is generally referenced herein to represent a DPLL circuit) that results in excellent DPPL vibration tolerance, vibration transfer and net vibration output performances, at lower band frequencies and higher band frequencies.
A filtering method for DPLL according to one embodiment of the present invention includes the steps of providing a first-in-first-out memory, then taking half-full of the memory as an ideal situation to define a ideal phase difference value between an input clock and a local recovery clock, calculating a read/write address difference of the first-in-first-out memory to define a phase difference between the input clock and the local recovery clock and comparing the phase difference with the ideal phase difference value. The filtering method further includes the steps of adjusting the local recovery clock in segments by taking the ideal phase difference value as a center; where at the segment where the ideal phase difference value is located, the local recovery clock follows the phase difference with a minimum changing speed; at other segments, the local recovery clock follows the phase difference with a changing speed increased segment by segment depending on a distance of the phase difference apart from the ideal phase difference value; at the segment apart farthest from the ideal phase difference value, the local recovery clock follows the phase difference with a maximum changing speed.
According to one aspect of the invention, the writing clock of the first-in-first-out memory is the input clock having been synchronized with a local crystal oscillator clock, and the reading clock of the first-in-first-out memory is the local recovery clock.
According to another aspect of the invention, adjusting the local recovery clock in segments by centered the ideal phase difference value is implemented by calculating a accumulated value through LF, which includes a phase sampling circuit samples the phase difference, where the LF calculates a accumulated value in segments according to difference between the phase difference sampled value and the ideal phase difference value. According to one aspect of the invention, if the phase difference deviates and the ideal phase difference value is larger, then the accumulated value follows the phase difference with a larger changing rate; if the phase difference deviates and the ideal phase difference value is smaller, then the accumulated value follows the phase difference with a small changing rate. Additionally, a digital frequency divider accumulates the accumulated value and the local recovery clock is received by controlling the local crystal oscillator dividing frequency. If the phase difference deviates and the ideal phase difference value is larger, then the local recovery clock increases the moving rate forward to the ideal value, which is larger; if the phase difference deviates the ideal phase difference value is smaller, then the local recovery clock moving rate is moved to a smaller ideal value.
According to yet another aspect of the invention, the digital frequency divider is implemented with an accumulator including an adder and a register, and their working frequency is provided by the local crystal oscillator. An integral part of the phase difference, inputted to the LF from said phase sampling circuit, is a read/write address difference, outputted from a subtracter, of the first-in-first-out memory, and the fractional part of the phase difference is output of the register of the digital frequency divider. The clock of the phase sampling circuit is a Frame signal (Fmclk) having been synchronized with the local crystal oscillator clock. The accumulated value may be a broken-lines continuous function of the phase difference.
Because the invention is based on DPLL, it can overcome weaknesses of APLL, which include large dispersion, high cost and low stability. The local recovery clock frequency (Fdco) of the present invention, which is outputted from the digital frequency divider, can adaptively adjust according to different frequency difference. When the phase difference between the input clock (Wclk) and the local recovery clock (Rclk) is far from the balance point, the local recovery clock frequency (Fdco) can move rapidly forward to nominal ideal frequency, but when the phase difference between the input clock (Wclk) and the local recovery clock (Rclk) is near the balance point, the local recovery clock frequency (Fdco) is adjusted with smaller rate. In this way, the present invention results in two advantageous important communication indicators: non-error code and minimized vibration, where vibration tolerance has been raised, the vibration transfer characteristic is good and net output vibration in low band frequency and high band frequency is improved over conventional circuits.


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International Search Report corresponding to International Application No. PCT/CN01/00068, dated Mar. 29, 2001.

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