Filtered register architecture to generate actuator signals

Details Filtered register architecture to generate actuator signals Filtered register architecture to generate actuator signals

2006-12-19

2009-11-17

Peugh, Brian R (Department: 2187)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S005110, C714S042000, C711S103000, C365S185090, C365S185330

Reexamination Certificate

active

07620859

ABSTRACT:
In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.

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