Filling an interconnect opening with different types of...

Details Filling an interconnect opening with different types of... Filling an interconnect opening with different types of...

2000-09-06

2002-05-14

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S660000, C438S672000, C438S675000

Reexamination Certificate

active

06387806

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of interconnect, such as copper interconnect for example, within an integrated circuit, and more particularly, to using different types of metal alloys for the seed layer and the conductive fill for filling an interconnect opening to minimize electromigration and void formation within the interconnect.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to
FIG. 1
, a cross sectional view is shown of a copper interconnect
102
within a trench
104
formed in an insulating layer
106
. The copper interconnect
102
within the insulating layer
106
is formed on a semiconductor wafer
108
such as a silicon substrate as part of an integrated circuit. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect
102
is typically formed by etching the trench
104
as an opening within the insulating layer
106
, and the trench
104
is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to
FIG. 1
, the insulating layer
106
may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. Copper may easily diffuse into such an insulating layer
106
, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material
110
is deposited to surround the copper interconnect
102
within the insulating layer
106
on the sidewalls and the bottom wall of the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material
110
is disposed between the copper interconnect
102
and the insulating layer
106
for preventing diffusion of copper from the copper interconnect
102
to the insulating layer
106
to preserve the integrity of the insulating layer
106
.
Further referring to
FIG. 1
, an encapsulating layer
112
is deposited as a passivation layer to encapsulate the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer
112
is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect
102
does not easily diffuse into such a dielectric of the encapsulating layer
112
.
Referring to
FIG. 1
, in the prior art, the encapsulating layer
112
of silicon nitride is deposited directly onto an exposed surface of the copper interconnect
102
and the surrounding insulating layer
106
after the exposed surface of the copper interconnect
102
and the surrounding insulating layer
106
are polished to a level surface. Unfortunately, the silicon nitride of the encapsulating layer
112
does not bond well to the copper at the exposed surface of the copper interconnect
102
.
Thus, although copper does not diffuse easily through the encapsulating layer
112
of silicon nitride, copper from the copper interconnect
102
laterally drifts from the interface between the copper interconnect
102
and the encapsulating layer
112
of silicon nitride along the bottom surface
114
of the encapsulating layer
112
of silicon nitride because of the weak bonding of the copper interconnect
102
and the encapsulating layer
112
of silicon nitride.
The copper that laterally drifts from the interface between the copper interconnect
102
and the encapsulating layer
112
of silicon nitride along the bottom surface
114
of the encapsulating layer
112
eventually diffuses into the insulating layer
106
to disadvantageously degrade the insulating property of the insulating layer
106
and to possibly degrade the copper interconnect electromigration life-time. Nevertheless, use of copper metallization is desirable for further scaling down integrated circuit dimensions because of the lower bulk resistivity and the higher electromigration tolerance. Thus, a mechanism is desired for preventing the drift of copper from the copper interconnect
102
into the insulating layer
106
.
In addition, typically for filling the trench
104
with copper, a seed layer of copper is deposited on the sidewalls and the bottom wall of the trench, and then copper is electroplated from the seed layer to fill the trench
104
in an ECD (electro chemical deposition) process, as known to one of ordinary skill in the art of integrated circuit fabrication. The seed layer of copper is typically deposited by a conformal deposition process such as a PVD (plasma vapor deposition) process or a CVD (chemical vapor deposition) process as known to one of ordinary skill in the art of integrated circuit fabrication. With such conformal deposition processes, referring to
FIG. 2
, when the aspect ratio (defined as the depth to the width) of an interconnect opening
120
to be filled with copper is relatively large (i.e., greater than 5:1), a seed layer
122
that is deposited on the sidewalls and the bottom wall of the opening
120
may have a significant overhang
124
at the top corners of the interconnect opening
120
.
Referring to
FIGS. 2 and 3
, when copper fill
126
is plated from the seed layer
122
, the copper that is plated from the overhang
124
may close off the top of the interconnect opening
120
before a center portion of the interconnect opening
120
is filled with copper to result in formation of a void
128
within the copper fill
126
toward the center of the interconnect opening
120
. Such a void
128
disadvantageously increases the resistance of the interconnect and may even contribute to electromigration failure of the interconnect.
Referring to
FIG. 4
, to minimize the overhang
124
at the top corners of the interconnect opening
120
, the seed layer of copper
122
is deposited to be thinner. However, the deposition of the seed layer
122
is not perfectly conformal with the seed layer
122
being even thinner at the sidewalls of the interconnect opening
120
. With such a thinner seed layer
122
, the thickness of the seed layer
122
may be as small as tens of angstroms at the sidewalls of the interconnect opening
120
, and granules
130
of agglomerated copper may form at the sidewalls of the interconnect opening
120
. Such granules
130
result in a discontinuous seed layer of copper
122
, and when copper is electroplated from such a discontinuo

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