Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-03
2001-04-03
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S598000, C716S030000
Reexamination Certificate
active
06211050
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method for fabricating integrated circuits. More particularly, the method utilizes patterned semiconductor layers, such as polycide and metal, to fill kerf (scribe) areas between chip sites (die) to prevent non-uniform insulating layers at the die corners during spin-on-glass (SOG) coating. The method and structure also prevent dishing during chemical-mechanical polishing of the SOG. The electrically conducting semiconductor (polycide and metal) layers that are patterned to make the integrated circuits are also patterned to provide the fill material in the kerf area, and therefore additional masking steps are not required.
(2) Description of the Prior Art
The integrated circuit density on ultra-large scale integrated (ULSI) circuits has dramatically increased due to advances in semiconductor processing, such as the use of high-resolution photolithography and anisotropic plasma etching. Therefore, the design rules are more aggressively scaled down, and in addition more levels of metal are added to effectively interconnect the high density of discrete devices on the chip. The patterned conducting layers are typically separated by insulating layers in which via holes are etched to interconnect the various levels of conducting (polysilicon and metal) interconnections.
To achieve this high circuit density in the die areas, it is necessary to use planar insulating layers. This allows distortion-free photoresist mask images to be formed on the planar surface with resolution and fidelity. Also the planar surface allows the conducting layers to be patterned by directional etching (e.g., anisotropic plasma etching) without leaving conducting layer residue in recesses that can cause intrametal electrical shorts on an otherwise non-planar surface.
One method for making planar insulating surfaces that is finding widespread use in the semiconductor industry is to deposit a spin-on glass (SOG) in liquid form by spin coating. The SOG is then baked and cured to form an inorganic silicon oxide (SiO
2
) layer that is then etched back or chemically-mechanically polished back. Generally, when the SOG is applied by spin coating, the layer is higher over closely spaced conducting lines than over areas with fewer metal lines. Therefore, the SOG is not completely planar. Also, when chemical-mechanical polishing (CMP) is used to polish back the SOG, the SOG over the area with the lower density of lines tends to polish back faster, resulting in recessing, and commonly referred to as a “dishing effect.”
One method of circumventing this non-uniform SOG problem on integrated circuits is described in U.S. Pat. No. 5,733,798 to Michael et al. The method utilizes non-operational conductors spaced at a minimum distance from each other to form a regular spaced arrangement of conductors in the die areas for integrated circuits. This allows the insulating layer over the patterned conductors to be polished back without dishing. Another method is described in U.S. Pat. No. 5,763,955 to Findley et al., in which polygon-shaped, metal-fill segments (dummy lines) are used to fill the spaces between the functional metal lines on the die areas for the integrated circuit to allow for global planarization on each of the die areas across the substrate. Bothra et al. in U.S. Pat. No. 5,618,757 describe a method in which dummy raised areas are formed in the gaps between the active conductive metal lines (traces). The dummy raised areas can be formed from the same metal layer used to form the conductive lines. This allows the SOG to be etched back to provide a planar surface.
When metal lines are spaced closely together (less than 1 micrometer) keyhole-type tunnels are formed unavoidably in the insulating layer over the metal lines. During processing, photoresist can be trapped in these tunnels at the end of the lines. Lur in U.S. Pat. No. 5,663,599 teaches a method of forming dummy metal lines at the end of the functional metal lines. This eliminates the keyhole in the insulating layer between the functional metal lines that would otherwise trap the photoresist during subsequent masking steps. Also, Lur teaches a method of forming partial via holes in which the metal lines terminate. This reduces the aspect ratio of the metal lines which eliminates the keyhole tunnel at the end of the metal lines. Mitwalsky et al. in U.S. Pat. No. 5,589,706 describe a method of making reliable fuse-link structures with vertical sidewalls by using dummy structures adjacent to the fuse, but the dummy structures do not form part of the fuse structure. Yamaha et al., U.S. Pat. No. 5,763,936, teach a method of reducing cracking in a thick spin-on-glass film which is used to hermetically seal the chip. The method involves forming dummy wiring patterns to thin the spin-on glass, thereby reducing stress in the spin-on glass.
However, another problem that is not addressed by the above references is the formation of non-uniform build-up of the SOG at the die (chip) area corners when spin-on glass (SOG) is applied by spin coating. This problem, commonly referred to as streaking, is best illustrated by referring to the prior art
FIGS. 1 through 5
. Typically an array of die (chip) areas are formed in which the integrated circuits are fabricated, separated by kerf or scribe areas. During processing, the kerf areas typically have test structures for inline testing, alignment marks, and the like. After the integrated circuits are completed, the substrate is diced through the kerf areas to separate the individual chips for packaging.
Referring to
FIG. 1
, a schematic three-dimensional aerial view is shown of a portion of a substrate
10
at the corners of four die areas
2
. During fabrication an electrically conducting layer
12
(such as polysilicon or metal) is deposited and patterned to form the integrated circuits (ICs) in the die areas
2
. To simplify the drawing and discussion, the detailed patterning of layer
12
to make the integrate circuits is not shown; only the edge of the patterned conducting layer
12
at the die edges is depicted. The patterned conducting layer is shown in
FIG. 1
prior to depositing a spin-on glass by spin coating. The array of die areas in which the integrated circuits are fabricated are separated by kerf areas (also called scribe areas)
4
.
To better appreciate the problem, a schematic cross-sectional view is shown in
FIG. 2
, through
2
-
2
′ of FIG.
1
. The cross section is shown through the kerf area
4
and through the patterned conducting layer
12
on die areas
2
and near the die corners A and B, respectively, after spin coating a spin-on-glass layer
16
. When the SOG
16
is dispensed on the rotating wafer, the result is a non-uniform layer that appears as streaking of the SOG at the corner A. As shown in
FIG. 2
, this SOG non-uniformity or streaking results in a thicker SOG at the die corner A, while the SOG is thinner at the corner B of the adjacent die. This non-uniformity results from the nature of the spin coating in which the directional flow F of the SOG is radially outward from the axis of rotation of the wafer due to the centrifuging effect. The SOG
16
is then baked and cured to reduce solvents and to form an essentially silicon oxide (SiO
x
) layer. As shown in prior-art
FIG. 3
, when this cured SOG layer
16
is etched back, the profile of the SOG layer, shown by the dashed line
18
, remains essentially unchanged, replicating the thicker portion (streaking) over corner A. However, overetching of the thinner SOG over the die area at corner B can result in damage to the patterned conducting layer
12
at the die edge.
Typically after spin coating and etching back the SOG, a conformal encapsulating layer (cap oxide layer)
20
, such as a chemical-vapor-deposited (CVD) silicon oxide, is deposited to seal the SOG layer. However, after the CVD oxide layer
20
is deposited, as shown in
FIG. 4
, and chemically-mechanically polished back, as shown in
FIG. 5
, dishing generally occurs in the kerf area
Chartered Semiconductor Manufacturing Ltd.
Le Vu A.
Pike Rosemary L. S.
Saile George O.
Wilson Christian D.
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