FIFO using asynchronous logic to interface between clocked logic

Details FIFO using asynchronous logic to interface between clocked logic FIFO using asynchronous logic to interface between clocked logic

1998-08-28

2000-10-03

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

326 63, 710 70, 712 36, G06F 1314, H03K 190175

Patent

active

061286788

ABSTRACT:
An asynchronous FIFO using Asynchronous NULL Convention LOGIC (NCL) to facilitate interfacing between multiple non-synchronous systems with a minimum of design and verification. Multiple interfaces, configurations, means for minimizing latency, and capabilities for datastream processing are also incorporated.

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